Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
Santa Clara , CA -- December 10, 2007 — Tensilica, Inc. today announced that it has added an optional full-speed, non-intrusive instruction trace capability to all of its Diamond Standard and Xtensa configurable processor cores. Tensilica’s TRAX-PC processor trace capture macrocell is Nexus 5001 compatible and ideal for debugging complex, challenging real-time applications such as engine and motor control. Software control and use of the on-chip TRAX hardware is fully integrated into Tensilica’s Xplorer integrated design environment (IDE) so software engineers can easily develop and debug programs while using the TRAX-PC trace macrocell.
Tensilica has been finding new interest in its processors in two areas involving real-time control. First, for standard control processors, the Diamond Standard processor family includes low-power, efficient 32-bit controllers. Particularly, the recently introduced Diamond Standard 106Micro, the smallest licensable 32-bit core, is very attractive to designers moving up from 8- and 16-bit controllers in these applications.
Second, Tensilica’s Xtensa configurable processors can be exactly configured and matched to the application. In many real-time applications, adding instructions to the processor that accelerate data processing can enable meeting the real-time constraints in a much more area and power efficient way versus traditional approaches of increasing the frequency (MHz) of the processor. This can allow a much smaller, lower-power, optimized Xtensa processor to replace a much bigger general-purpose processor core.
“Difficult debugging problems are sometimes caused by subtle interactions between subsystems and other timing consideration in hard real-time systems. State-of-the-art processor trace tools can ease system integration, solidify product schedules and accelerate revenues,” stated Chris Rowen, Tensilica’s president and CEO. “By adding trace capability, designers can feel confident in their ability to debug and deploy FPGA prototypes or SOC silicon solutions.”
Tensilica’s TRAX-PC processor trace capture block is an optional item for use with all Tensilica Diamond Standard and Xtensa processors. It provides tracing information through an SoC’s JTAG debug port without requiring added device pins. It helps designers trace all changes in program flow including exceptions and interrupts. The trace block uses a circular on-chip trace buffer with user-defined sizing to capture the trace stream and accepts PC-based triggers and external trigger inputs.
Tensilica’s associated software tools convert the compressed trace into an annotated program disassembly for easy debugging. These tools are fully integrated into Tensilica’s world-class Eclipse-based, Xtensa Xplorer™ integrated design environment (IDE). The Xplorer IDE provides a powerful visualization and debugging environment to both develop and debug programs using the TRAX-PC trace macrocell.
The TRAX-PC processor trade capture macrocell is available now for use with all current Tensilica processor products.
Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.