Sidense Broadens OTP Offering with Additional Process Nodes at SMIC
Update: Synopsys Expands DesignWare IP Portfolio with Acquisition of Sidense Corporation (Oct. 17, 2017)
Customers Now Have Wider Access to Industry’s Smallest Footprint, Lowest Power and Highest Performance OTP IP
Ottawa, Canada and Shanghai, China - Dec. 21, 2007 - Sidense, a leading developer of Logic Non-Volatile Memory (NVM) IP cores, today announced that its one-time programmable (OTP) technology is available on Semiconductor Manufacturing International Corporation’s (SMIC) 180nm and 90nm processes.
Demand for OTP memory is growing rapidly in many applications and usages such as consumer electronics products, wireless products, code storage, product configuration, and trimming of analog circuits. “We are experiencing very strong demand for our OTP IP for chips processed from 180nm to 65nm,” said Steven Cliadakis, VP of Worldwide Sales at Sidense. “By working with SMIC, we are able to provide our customers with additional access to our IP at one more leading foundry.”
Many of today’s designs require very low power and cost-effective solutions. “Sidense’s OTP IP will allow our customers to meet their very aggressive power targets,” said Henry Liu, Senior Director, Design Services Division at SMIC. “Additionally, Sidense’s OTP is very small, which allows our customers in competitive markets, such as the consumer space, to achieve their low-cost goals.”
About Sidense
Sidense provides secure, dense and reliable non-volatile one-time programmable (OTP) memory IP for use in standard-logic CMOS processes, with no additional masks or process steps required. Sidense's patented one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint and lowest power Logic Non-Volatile Memory (NVM) solution.
Sidense OTP memory is available at 180nm, 130nm, 90nm and 65nm and scalable to 45nm and below. Ideal applications include analog trimming, code storage, encryption keys such as HDCP, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, visit www.sidense.com.
|
Related News
- Sidense to Deliver OTP Cores in UMC's 90nm and 65nm Process Nodes
- Sidense First to Offer Antifuse OTP Supporting 1.8V IO in 40nm and 28nm Process Nodes
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass-Produced
- CFX announces commercial availability of anti-fuse OTP technology on 90nm CIS process
- SkyWater Announces Availability of SRAM Memory Compiler for 90 nm Strategic Rad Hard by Process Offering
Breaking News
- TSMC September 2024 Revenue Report
- Crypto Quantique teams up with Attopsemi to simplify the implementation of PUF technology in MCUs and SoCs
- Intel, TSMC to detail 2nm processes at IEDM
- SensiML Expands Platform Support to Include the RISC-V Architecture
- MIPI Alliance Announces OEM, Expanded Ecosystem Support for MIPI A-PHY Automotive SerDes Specification
Most Popular
- Deeptech Keysom completes a €4M fundraising and deploys the first “no-code” tool dedicated to the design of tailor-made processors
- Bluetooth® V6.0 Channel Sounding RF Transceiver IP Core in 22nm & 40nm for ultra-low power distance aware Bluetooth connected devices
- Secure-IC unveils its Securyzr™ neo Core Platform at Embedded World North America 2024
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Electronic System Design Industry Posts $4.7 Billion in Revenue in Q2 2024, ESD Alliance Reports
E-mail This Article | Printer-Friendly Page |