MOUNTAIN VIEW, Calif. Synopsys Inc. is taking the wraps off its second-generation design-for-test technology and is telling users they now can achieve "DFT closure."
Synopsys calls DFT closure the next step in design for test, and defines it as the ability to meet all mandated testability requirements spanning register-transfer level to GDSII tapeout with no costly back-end design iterations.
DFT Compiler, Synopsys' new one-pass test synthesis package, replaces its predecessor, Test Compiler, and sets out to make its reputation at the RT level. There, it performs design rule checking (via the component, RTL TestDRC), feeding back information that lets designers fix testability problems in the high-level source code.
If a designer would rather let the tool do the repairs, then the AutoFix portion of DFT Compiler takes over. After synthesis, AutoFix heads down to the gate level, where it automatically identifies common violations , such as a lack of clock controllability or troublesome asynchronous set/reset signals.
AutoFix then proceeds to insert test logic, keeping timing, power and area needs in mind.
To make testability a start-to-finish affair and achieve optimal DFT closure and design constraints, Synopsys has meshed its test tools with its design and verification flows. Thus, DFT Compiler forms a tight bond with Design Compiler, TetraMAX ATPG and BSD Compiler (for boundary scan).
"DFT closure brings a level of predictability," said Farhad Hyatt, vice president of marketing at Synopsys, "and is what is needed to address DFT in the next generation of complex designs."
Of course, closure implies a certain high degree of thoroughness and accuracy. To achieve those, DFT Compiler eschews earlier static approaches and, instead, opts for dynamic simulation-based techniques in its quest to provide comprehensive rules checking.
As a result, DFT Compiler can identify, verify and cover a wide set of testability rul es that can be checked at the RT level. It achieves consistency with downstream gate-level DRCs to avoid false violations that can cause iterations late in the design; and it supports VHDL and Verilog, with feedback on the sources of violations in the native language of the design.
To help wade through what could be thousands of lines of code, the tool flags the violations and describes them, pointing to the relevant lines of RTL code. Helping even further, the error report is in easily browsed HTML. Users can control the number and type of messages displayed.
Most of the rules checked by RTL TestDRC are prescan DRCs that cover common violations, such as those that prevent scan insertion (uncontrollable clocks or asynchronous set/reset to flip-flops) or data capture (clocks driving flip-flop data pins) or reduce fault coverage (combinational feedback loops).
In doing its job, RTL TestDRC simulates the test initialization constraints, setting up the constraints by using any existing test-synthesis commands.
As part of its search for a formal approach to testability analysis, S3 Inc. has evaluated RTL Test DRC's capabilities. According to DFT manager Meh-ron Amerian, Synopsys has enabled RTL designers to identify problems prior to synthesis and fix them within the synthesis environment.
"This significantly cuts down on costly back-end iterations due to testability problems and enhances design-team productivity," Amerian said.
Design iterations still may be necessary, according to Synopsys' Hyatt, but they take place up front, where they are fewer and much more manageable. A survey conducted by Synopsys shows that trying to fix test violations late can seriously affect the design cycle, with iterations eating up two days to two months of valuable time.
Also, the ability to deal with DRCs at the gate level is an inverse function of design size and complexity. Synopsys notes that a 500,000-gate design can have between 5,000 and 10,000 rule violations, re quiring 2,000 to 3,000 test points for a fix.
Others have evaluated the AutoFix feature. Catherine Chow, a principal engineer at DataPath Systems, designs mixed-signal communications and storage chips for the company. "AutoFix saved me a month's time," she said, "and the frustration of trying to fix test DRC violations manually. It was easy to use and integrate into our design methodology."
AutoFix focuses mainly on the controllability of clocks and asynchronous set/reset signals. During the fixing process, the tool ensures that timing constraints are met and that the net-list is testable and ready for automatic test pattern generation.
Synopsys said it would release DFT Compiler in May as an option to the Design Compiler synthesis software. Existing test-synthesis customers will receive the new capability under their update contracts. New licenses for DFT Compiler start at $10,000.