The repairable memory solution with BIST test interface option is optimized in low leakage design, enabling low power and memory-intensive 65nm SoC.
Hsin-Chu, Taiwan, Jan 31, 2008 -- Faraday Technology (TAIEX: 3035) today announced the availability of the advanced memory compiler in UMC 65nm LL process. The 65nm LL memory solution features row redundancy, BIST test interface (BTI) and programmable sensing margin for manufacturing yield, and full-chip routability enhancement. Faraday's 65nm LL memory compiler is silicon-proven and is now available to its customers.
At 65nm, due to its higher cost, applications will be targeted at mainstream market, such as wireless, consumer electronics, HD video/image and PON. These applications are complex SoC design and can use hundreds of memories for video/network data processing. The use of 65nm technology provides good memory density. However, due to process variation and higher design complexity, the magnitude of memory leakage, yield loss and wiring congestion become major concerns and big challenges for designers. With experienced memory design capability, DFM (design-for-manufacturing) and power-aware design methodology, Faraday is able to deliver new features in the 65nm memory compiler to address these challenges.
"We are very glad to provide the first memory compiler in UMC 65nm LL process," said Hsin Wang, Vice President of Sales at Faraday. "The repairable and low-leakage memory solution is designed for 65nm SoC that demands high density and low power. It enables our customers to be competitive on the market with lower power consumption, smaller size and higher level of integration. To date, 3 customers are designing in Faraday's new 65nm memory solution," he added.
Faraday's 65nm memory compiler is optimized in UMC's low leakage process. It allows users to generate a variety of memory options, including words, bits and aspect ratios, while retaining desirable area, performance, and power specification. A 4Kx16 memory provides 20~40% less the leakage ratio of 90nm SP with 50% area reduction and 20% performance improvement. In addition, Faraday memory compiler provides optimized features for design-for-manufacturing (DFM); Built-in 2-row redundancy and programmable sensing margin are implemented for yield improvement. To facilitate chip-level integration, an optional BIST test interface (BTI) is provided for better routability, which will also reduce overall chip size by eliminating the use of memory routing channel.
"Migrating to the deep submicron process, memory design is becoming more complicated due to the device variability and increased array redundancy," said Victor Lin, Vice President of IP R&D & Project at Faraday. "The new 65nm LL memory compiler keeps a high level of memory yield and reliability. In addition, its built-in function options and programmability allow easy design integration for our customers."
Faraday's memory compiler for UMC 65nm LL process is now available. High speed version for performance SoC will be available in Q3, 2008.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad silicon IP portfolio includes Cell Library ,Memory Compiler,ARM-compliant CPUs, DDRII, MPEG4, H.264, USB 2.0, 10/100 Ethernet, Serial ATA, PCI Express, and UWB . With more than 800 employees and 2007 revenue of US$ 156 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan , Faraday has service and support offices around the world, including the U.S. , Japan , Europe, and China . For more information, please visit : www.faraday-tech.com