Industry-Standard DDR Memory System Specification Delivers Increased Interoperability and Support for DDR3
PALO ALTO, Calif., February 08, 2008 — Denali Software, Inc., today, on behalf of all DDR PHY Interface (DFI) specification participating members, including representatives from industry-leading companies ARM, Denali, Intel, and Samsung, announced the release of the latest DFI specification version 2.0. The growing community of technology experts and interface users are invited to comment and provide feedback to the specification before its formal release within the next 30 days. System developers, memory controller vendors, and PHY providers can benefit from the increased interoperability and use of new DDR3 features such as read and write leveling, thereby accelerating DDR memory system deployment and reducing the significant integration and verification costs. This enhanced version of the DFI specification will be highlighted this week in the Denali booth (#322) at DesignCon in Santa Clara, CA.
"With the rapid adoption and benefits realized from the initial DFI specification, the DFI working group has been concentrating their efforts on improving the specification for increased integration and verification between the PHY and memory controllers," said Bryan Jones, IP outsourcing program manager, Mobility Group, Intel Corporation. "The additional inputs from the community will improve the existing expanded specification and significantly minimize the design and integration cost benefits attributed to the reusable IP in this space."
Since last year's International Engineering Consortium DesignVision award for the 1.0 specification, over 1000 engineers from over 500 companies have downloaded the specification. The DFI specification 2.0, built on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs, allows designers a standard that has wide industry acceptance and be confident that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing the reuse of the individual components that make up the memory system. Submit all comments to the DFI 2.0 specification by March 5 at: www.ddr-phy.org.
"We realize the need to evolve the specification and gather the best technical contributions from around the world," said Brian Gardner, vice president of IP products at Denali. "With such a large and diverse community behind this initiative, it represents the best example of a successful standardization process; one where users, vendors, and even competitors work together toward a shared goal."
About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, visit: www.ddr-phy.org.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.