SANTA CLARA, Calif. The dream of engineers surfing the Web to find intellectual property (IP) cores is likely to remain just that, according to a keynote speech delivered at IP2000 on Tuesday (March 21) by Theo Claasen, chief technology officer of Philips Semiconductors.
"A lot of IP reuse has failed," Claasen said. "The massive browsing of the Net to find IP and place it is not happening today. In my opinion, it won't happen in the future."
However, without extensive IP reuse, the products needed for next-generation consumer products will not be made, Claasen said.
"The technology design gap is growing at 60 percent," he said. "The only way to close that gap is by reuse of IP. I mean chips made up of 95-to-99 percent IP blocks. That's the only way to get chips out in six-to-nine months."
Claasen recommended the use of architectural frameworks to constrain the interfaces between blocks and ease their integration. Largely oriented towards vertical-market applications, these frameworks will enforce specific bus protocols and interfaces to make chip assembly and verification less troublesome.
"Today, and tomorrow, reuse of blocks within different architecture frameworks will be very cumbersome to say the least," Claasen said.
"A rigid methodology is much more than a technical problem. It requires management attention so that designers are forced to work with guidelines and standards within the architectural framework that companies have chosen. You have to constrain it to certain application domains. The constraints will be different in various application domains," he said.
Philips has combined several initiatives to promote the idea of architectural frameworks. The rapid silicon prototyping (RSP) platform developed by VLSI Technology puts a large number of IP cores onto a single chip. The cores can be turned off or 'deconfigured' if they are not needed for a particular design.
Philips created an IP program called CoReUse, designed to control the quality of cores in its portfolio, which includes blocks developed by Mentor Graphics' Inventra subsidiary. Many of these cores are delivered using integrator software, called HDL-I, that generates the cores themselves and simulation models automatically.
The company is working on a new version of the RSP system that can accommodate the two main processor families that the company supports. Philips has a license to the MIPS processor and now has one for ARM through its acquisition last year of VLSI Technology.
"With all of the IP that we have in Philips, to make a single prototyping platform would be rather cumbersome," Claasen said. "The use of applications platforms can help us reduce the number of IP cores that we need to integrate."
Since beginning its CoReUse program in 1997, Philips has amassed 250 cores in its IP repository and is expecting the number to grow.
"We have now started the IP program and challenged the business groups to make their cores compliant with CoReUse," said Claasen.
Philips could open up its CoReUse program to third parties, which could deposit cores into the Philips repository, Claasen said. However, there are potential problems in determining whether cores are compliant. Philips took responsibility to ensure that the Inventra cores were compliant, for example.
"To the level of control to which people are compliant, we need to have authentication," Claasen said. "We need to have the issue cleared of who will be liable if [the core] is not [compliant] in the end."
Chris Edwards is a contributing editor to Electronics Times, EE Times' sister publication in the United Kingdom.