English
SiliconBlue 65-nm FPGAs run on microamps
Peter Clarke, EE Times
(03/07/2008 11:42 AM EST)
LONDON — SiliconBlue Technologies Corp. (Sunnyvale Calif.) is offering a family of low-power FPGAs implemented on a 65-nm CMOS manufacturing process. The FPGAs, which carry their own non-volatile memory on-chip for holding configuration data, come in small ball grid array packages and are intended for use in mobile phones and other handheld devices.
The company was founded by Kapil Shankar, CEO, a 20-year veteran of the programmable logic industry, and Antti Kokkinen, a partner and cofounder of venture capital firm BlueRun Ventures (Menlo Park, Calif.).
(03/07/2008 11:42 AM EST)
LONDON — SiliconBlue Technologies Corp. (Sunnyvale Calif.) is offering a family of low-power FPGAs implemented on a 65-nm CMOS manufacturing process. The FPGAs, which carry their own non-volatile memory on-chip for holding configuration data, come in small ball grid array packages and are intended for use in mobile phones and other handheld devices.
The company was founded by Kapil Shankar, CEO, a 20-year veteran of the programmable logic industry, and Antti Kokkinen, a partner and cofounder of venture capital firm BlueRun Ventures (Menlo Park, Calif.).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Altera Shipping Full Line of 65-nm Cyclone III FPGAs
- Impinj preps 65-nm NVM for October launch
- Synopsys Achieves Two IP Firsts: 65-nm PCIe and 90-nm USB Compliance Utilizing Common Platform Technologies
- A panel discusses 65-nm mixed-signal design
- Synopsys Enables STMicroelectronics to Achieve First-Silicon Success for 65-nm Dual High-Definition MPEG-4 Decoder
Breaking News
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Cadence Announces Most Comprehensive True Hybrid Cloud Solution to Provide Seamless Data Access and Management
- Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
- Cadence Collaborates with MemVerge to Increase Resiliency and Cost-Optimization of Long-Running High-Memory EDA Jobs on AWS Spot Instances
- M31 Successfully Validates 5nm IP Solution to Empower Global AI Applications
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance