DualSoft announces Industry's First Automatic Document Generation Utility for Verilog and VHDL Designs
March 20, 2000 - Nashua NH - DualSoft today announced the release of HDLDoc[tm], a document generation utility for Verilog and VHDL designs. HDLDoc is targeted for Design houses and IP developers who need to develop and publish consistent documentation about their HDL designs for internal and/or external customers. HDLDoc automatically generates an HTML or textual summary of the entire design by reading and analyzing the design to determine design hierarchy, reset methodology, clocking mechanism and many other design-specific attributes.
"We are proud to announce the immediate availability of HDLDoc ", said Sashi Obilisetty, chief executive officer, DualSoft LLC, "This tool aims to enable enterprise-level reuse by allowing IP and System integrators to quickly determine the suitability of an IP block without needing to go through thousands of lines of code; it is well-positioned to be a key component in any Reuse-based design methodology."
"HDLDoc is a robust utility that will aid design engineers tremendously in publishing their designs in a browser-ready format", said Saurin Shroff, vice president of engineering, DualSoft LLC, "We developed it with the engineer in mind. Using HDLDoc, the engineer can write the documentation only once, right in the HDL source. HDLDoc will create a web-ready document by analyzing the HDL source. Engineers will find that this tool allows them to be more productive by automating the routine, but necessary task of design documentation."
Figure 1 : HDLDoc Environment
HDLDoc reads Verilog or VHDL designs and creates web-ready design documents that contain essential details of the design such as port interface, hierarchy, clocking style and reset methodology. The tool creates "intelligent" documentation by inferring important clock and reset details. It locates and extracts key comments written by the designer to describe the intent of design. It runs in both command-line and GUI mode. The output can be created as HTML or text documents, which may then be placed directly on the company's IP/Design Intranet.
The most common use of HDLDoc is in a project environment, where IP needs to be systematically documented after design completion, to facilitate IP use (and reuse) by collaborating design teams. Document generation by HDLDoc can be used as the sign-off step, after the design team has designed, implemented and tested the IP. The document generated by HDLDoc can then be published on a central site or exchanged via electronic transmission.
HDLDoc is also useful to design services and consulting organizations, where it can be used to create an easy-to-read delivery document(s).
HDLDoc will be improved continuously to be compliant with Industry documentation standards. Compliance with Motorola's Semiconductor Reuse Standard (SRS) documentation standard and VSIA's Virtual Component Transfer Specification is currently under development.
Because of its inherent value in existing design flows, development is underway to achieve tighter integration with both DualSoft and other complementary tools. Plans also include XML support and additional high value content generation.
HDLDoc will start shipping in mid-April, 2000. Beta versions and evaluation copies are available on request. HDLDoc is Java-based and available on all Java-compatible platforms. Companies interested in OEM partnerships or Joint Marketing Agreements may contact Sashi Obilisetty at 603 891 0225.
DualSoft develops and markets enterprise-level Reuse-centric tools for EDA. Products include ReviewVer[tm], a design rule checker for Verilog, SuperLint, a Verilog Linter and JADES, a Verilog analyzer in 100% Pure Java. More information about the company and its products may be found at www.dualsoft.com.
HDLDoc, SuperLint, ReviewVer and JADES are trademarks of DualSoft LLC. All others are trademarks or registered trademarks are the property of their respective owners.