SoC Design Productivity Enhancement from YXI: XE Tool Suite version 1.3
Y Explorations, Inc. (YXI), innovator of Reuse Automation[tm] tools for SoC design through IP selection and IP interface synthesis technology, announces XE Tool Suite version 1.3.
SoC design productivity hinges on two essential methodology changes: first, describing designs at a higher-level of abstraction utilizing the behavioral and architectural description capabilities built into the VHDL and Verilog Design Languages; and second, targeting much larger pre-verified design elements than the simple gates and registers re-used through traditional logic synthesis tools. Raise the design abstraction level AND the complexity of re-used components in SoC design. Complex IP components can be automatically inferred, instantiated and scheduled in SoC designs by YXI's version 1.3 enhanced architectural synthesis engine and IP interface RTL netlist generation tool, eXplorations Environment (XE).
XE tools provide a complete infrastructure for IP-based design with database, architectural exploration and interface synthesis tools. XE is scalable to support multinational corporations' shared (and secured) IP databases down to small design team's reusable components.
This v1.3 release of XE tools includes enhancements for:
1. Capturing and documenting IP components at any level of abstraction.
2. Specifying IP usage modes by the developer (called IP Sign-Off), limiting maintenance and support liabilities.
3. Organizing these IP in an open and extensible database structure.
4. Presenting potential IP based SoC solutions plotted against key design trade-off parameters.
5. Synthesizing interface logic for requested combinations of IP.
Featured in this release is a common Kernel for both Verilog and VHDL input, allowing Verilog users to exploit YXI's automatic reuse functions. Verilog can now be used for SoC architectural exploration providing IP selection, IP instantiation, IP component inference and macros using both RTL and super-state models.
YXI's IP Developer's Kit (IPDK) captures IP for automated reuse and features an improved GUI interface and allows documenting and synthesizing with a greater range of functional characteristics. IPDK has an enhanced ability to handle data-selection functions (e.g. Multiplexers) and complex IP initialization sequences for microprocessor and programmable DSP cores. Increased modeling style flexibility now accepts cycle-accurate behavioral descriptions, as well as Synopsys' Design Compiler(TM) and Behavioral Compiler(TM) modeling styles.
The eXplorations Tool Suite, v1.3, is available now for purchase and as an upgrade to licenses presently under maintenance.
About Y Explorations, Inc.
Founded in 1995, YXI (www.yxi.com) delivers Reuse Automation[tm] tools and methodologies exploiting system level synthesis methodologies enabling Systems-on-a-Chip (SoC) creation from IP elements an order of magnitude faster than existing RTL design approaches. Semiconductor core developers, distributors and integrators use YXI tools in each facet of the burgeoning IP reuse and exchange industry.
The company is located in Orange County, CA's Spectrum Technology Center at:
20902 Bake Parkway, Suite 100, Lake Forest, CA 92630.
Telephone (949) 457-0294, Fax (949) 457-0437,