TSMC First to Deliver 40nm Process Technology
Hsinchu, Taiwan, R.O.C. - March 24, 2008 - Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today unveiled the foundry’s first 40 nanometer (nm) manufacturing process technology.
The new node supports a performance-driven general purpose (40G) technology and a power-efficient low power (40LP) technology. It features a full design service package and a design ecosystem that covers verified third party IP, third party EDA tools, TSMC-generated SPICE models and foundation IPs. First wafers out are expected in the second quarter of 2008.
Highlights:
- A 2.35 times raw gate density improvement over 65nm
- Active power down-scaling of up to 15% over 45nm
- Smallest SRAM cell size and macro size in the industry
- General Purpose and Low Power versions for broad product applications
- Dozens of customers in the design pipeline today
- Frequent and regular CyberShuttleTM, MPW prototyping running
“Our design flow can take designs started at 45nm and target it toward the advantages of 40nm,” said John Wei, senior director of Advanced Technology Marketing at TSMC. “A lot of TSMC development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives,” he said.
TSMC has developed the 40LP for leakage-sensitive applications such as wireless and portable devices and its 40G variant targeting performance applications including CPU, GPU (Graphic Processing Unit), game console, networking and FPGA designs and other high-performance consumer devices. The 40nm footprint is linearly shrunk and the SRAM performance is fully maintained when compared to its 45nm counterpart, its SRAM cell size is now the smallest in the industry at 0.242µm2.
A full range of mixed signal and RF options accompany the 40G and 40LP processes along with Embedded DRAM, to match the breath of applications that can take advantage of the new node’s unbeatable size and performance combination.
The 40nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. The logic family includes a low-power triple gate oxide (LPG) option to support high performance wireless and portable applications. Both the G and the LP processes offer multiple Vt core devices and 1.8V, 2.5V I/O options to meet different product requirements.
TSMC’s CyberShuttle prototyping service can be booked for 40nm designs in April, June, August, October and December this year and first wave 45/40nm customers have already used above 200 blocks on completed multi-project wafer runs. The 40G and LP processes will initially run in TSMC’s 12" wafer Fab 12 and will be transferred to Fab 14 as demand ramps.
About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2007 exceeded eight million (8-inch equivalent) wafers, including capacity from two advanced 12-inch Gigafabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.
|
Related News
- Virage Logic First to Deliver Complete Memory Compiler and Logic Library IP Portfolio for TSMC 40nm Process
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Flex Logix EFLX 1K eFPGA Core Design Kits Available Now For TSMC 40nm ULP And 40nm LP Process Technologies
- TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology
- QuickLogic Announces eFPGA Now Available on TSMC 40nm Process
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |