0-In Design ships verification tool

0-In Design ships verification tool
By Richard Goering, EE Times
March 13, 2000 (2:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000313S0027

SAN JOSE, Calif. — After nearly a two-year hiatus, 0-In Design Automation has announced the first production release of 0-In Check, a "white box" verification tool that creates and executes checkers in HDL test suites. 0-In Search, a follow-on product, is set for second-quarter release.

After 0-In Check was first announced in June 1998, the company found that the initial low-level checks, which were automatically synthesized, weren't sufficient. Since then, 0-In has created the CheckerWare library of more-sophisticated tests that require some user direction.

"The lower-level tests were not catching the types of bugs our partners were finding, so we went back and built a large library of directive tests that use designer hints to get the tests built," said Curt Widdoes, chief executive officer at 0-In.

Designers start the checkers by embedding directives in RTL code. Directives call checkers from the lib rary and tell how to configure them. For a FIFO checker, for example, a designer would identify the FIFO and the signals that control it.

Design monitored

0-In Check then reads the RTL code, configures the checkers for the current version of the RTL design and generates Verilog files implementing the checkers. These files can run with Verilog simulators from Cadence Design Systems Inc. or Synopsys Inc. Checkers monitor the design during simulation and report any violations. Overhead depends on the number of checks, but is typically around 15 percent, Widdoes said.

The purpose of 0-In Check is to test for corner cases that are unlikely to be found by simulation. CheckerWare tests, for instance, can ensure data is used before it's overwritten, or that data isn't written into a full or empty FIFO. More complex checkers have been developed for several standard interfaces, including PCI, Utopia and SDRAM. CheckerWare is provided in Verilog source, so designers can add their own proprietary checkers.

0-In Search turbocharges 0-In Check by using formal-verification technology to fire the checkers. "0-In Search will take the testbench and try billions and billions of alternative ways of stimulating the design," said Widdoes.

0-In Check is available now on Unix platforms for $25,000, including CheckerWare. 0-In Search, which requires O-In Check, will be priced at the production release.