PHOENIX -- Just when chip designers are learning to cope with first-generation system-on-chip (SoC) complexities, the Summit Conference of Semico Research Inc. this week was told that many of these solutions will no longer work.
Walden Rhines, president and CEO of Mentor Graphics Corp. in Wilsonville, Ore., said that right now chip designers worry about "how fast can transistors switch in a circuit." The new paradigm, he added, is "how fast can the the signal be transmitted from one transistor to another on the chip."
He also warned that with each die shrink, the coupling of interconnects with possible interference and noise effects "becomes a paramount concern. Designers have to crank in new tools every time they go down to smaller design rules."
He asserted that die shrinks may involve new lithography techniques, such as optical proximity correction (POC) or phase-shift masks. "Existing chip designs will have to be recycled to accommodate the new optical techniques. And each recycling is a chance to screw up an existing chip design," he warned.
Rhines also said that chip makers who traditionally use only one design language now must find ways to deal with different cores on a chip developed with different languages. "Increasingly designers are integrating cores developed with VHDL with cores using Verilog."
The design-tool executive also said various design teams in the development of a chip "must work more closely together from the very start." He warned that often engineers transforming the design to a gate-level description pass on open issues to engineers in the next transformation step to the physical description. However, he said, at the physical layout, all the earlier design problems have mounted up so a complex circuit "frequently just can't be done."