English
Accelerating development and lowering risk
By Gabe Moretti
April 15, 2008 -- edadesignline.com
The central message of this panel was that the industry must grow from being centered on IP blocks to offer and use IP subsystems. Bill Martin, who chaired the panel stated that the intention should be to remove many of the integration issues design teams struggle with in the effort to meet market introduction deadlines. Mr. Martin observed that in too many cases, engineers want to modify third party IP. But doing this results in destroying the value built into the IP. So tinkering not only raises many verification and support problems, but lowers the value of the IP, resulting in significant inefficiency and thus much higher costs.
Peter Hirt, of ST Microelectronics gave an example of a set top box that has 100 Million transistors, targets the 65 nm process node and is scheduled to be fabricated at 55 nm with optical shrink technology. The connectivity subsystems inside the chip have presented a particular challenge involving connecting third party IP blocks with logic developed in-house.
April 15, 2008 -- edadesignline.com
The central message of this panel was that the industry must grow from being centered on IP blocks to offer and use IP subsystems. Bill Martin, who chaired the panel stated that the intention should be to remove many of the integration issues design teams struggle with in the effort to meet market introduction deadlines. Mr. Martin observed that in too many cases, engineers want to modify third party IP. But doing this results in destroying the value built into the IP. So tinkering not only raises many verification and support problems, but lowers the value of the IP, resulting in significant inefficiency and thus much higher costs.
Peter Hirt, of ST Microelectronics gave an example of a set top box that has 100 Million transistors, targets the 65 nm process node and is scheduled to be fabricated at 55 nm with optical shrink technology. The connectivity subsystems inside the chip have presented a particular challenge involving connecting third party IP blocks with logic developed in-house.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Microchip FPGAs Speed Intelligent Edge Designs and Reduce Development Cost and Risk with Tailored PolarFire® FPGA and SoC Solution Stacks
- StarFive VisionFive Single Board Computer Officially for Sale, Accelerating RISC-V Ecosystem Development
- eVaderis collaborates with Mentor on accelerating eMRAM IPs and Compilers development
- Spectral Edge appoints new CTO, accelerating development of smartphone imaging technology
- EnSilica launches the eSi-ZM1 System-on-Module for faster, lower risk and smarter embedded systems development
Breaking News
- Launching MosChip DigitalSky™ for Building Connected Intelligent Enterprises
- Crypto Quantique collaborates with ADLINK to simplify and enhance device security in industrial PCs
- Xiphera Partners with IPro for the Israeli Chip Design Market
- Siemens collaborates with GlobalFoundries to certify Analog FastSPICE for the foundry's high-performance processes
- EXTOLL collaborates with Frontgrade Technologies for High-Speed SerDes IP
Most Popular
- BrainChip Introduces Lowest-Power AI Acceleration Co-Processor
- Launching MosChip DigitalSky™ for Building Connected Intelligent Enterprises
- Siemens collaborates with GlobalFoundries to certify Analog FastSPICE for the foundry's high-performance processes
- RaiderChip brings Meta Llama 3.2 LLM HW acceleration to low cost FPGAs
- Crypto Quantique collaborates with ADLINK to simplify and enhance device security in industrial PCs