Virage Logic Strengthens Low Power IP Product Portfolio with Availability of 65nm CPF-Enabled Ultra-Low-Power Standard Cell Libraries
FREMONT, Calif.-- April 17, 2008 --Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner and pioneer in Silicon Aware IP™, today announced the availability of Common Power Format (CPF) enabled 65-nanometer (nm) Standard Cell logic libraries. Virage Logic’s 65nm Ultra-Low-Power (ULP) product offering will help enable customers to manage low-power design projects targeting applications in the rapidly expanding mobile consumer market which require advanced power-lowering design techniques such as power shut-down, state retention and multiple voltage islands.
Virage Logic’s SiWare™ Logic Ultra Low-Power Standard Cell libraries now include CPF technology views that identify specialized cells available in the library to enable advanced power saving capabilities. Included are always-on cells, isolation cells, level shifter cells, power switch cells and state retention cells to support a full range of advanced low-power techniques. CPF, a Silicon Integration Initiative (Si2)-standard power intent format, is used for specifying power-saving techniques early in the design process, thereby allowing sharing and reuse of low-power intelligence throughout the design process. CPF enables all design, verification, implementation, and technology-related power objectives to be captured early in the design process and allows for application of that data consistently from RTL to GDSII for improved designer productivity.
“We are seeing increasing demand for CPF support from our customers who wish to minimize chip power consumption,” said Brani Buric, vice president of product marketing and strategic foundry relationships for Virage Logic. “As an integral part of the SoC design ecosystem, we are delivering CPF with our libraries to help our customers unambiguously define power management intent up front in the design process and shorten their design cycles.”
“We are pleased that Virage Logic is providing pre-qualified CPF-enabled logic libraries to customers adopting advanced power-saving design techniques,” said Pankaj Mayor, group director, business enablement at Cadence Design Systems. “Using the Cadence Low-Power Solution and Virage Logic libraries, customers will be able to take advantage of productivity gains and meet their low-power product design requirements.”
Virage Logic has completed its first customer delivery of the 65nm libraries and expects to expand CPF support to other advanced node libraries based on customer request throughout the year.
About SiWare Logic Libraries
The SiWare Logic product line includes yield-optimized standard cells for a wide variety of design applications with multiple threshold process variants. SiWare Logic libraries are offered using three separate architectures to optimize circuits for Ultra-High-Density, High-Speed, or general use. SiWare Ultra-Low-Power extension libraries provide designers with the most advanced power management capabilities.
About Virage Logic
Founded in 1996, Virage Logic Corporation (NASDAQ:VIRL) rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Today, as the semiconductor industry's trusted IP partner, the company's Silicon Aware IP offering (embedded memories, logic libraries and I/Os) includes silicon behavior knowledge for increased predictability and manufacturability. Through its recent acquisition of Ingot Systems, the company has expanded its product offering to include Application Specific IP (ASIP) solutions such as Double Data Rate (DDR) Memory Controllers and design services. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, computer and graphics, automotive, and defense markets. The company uses its FirstPass-Silicon Characterization Lab™ for certain products to help ensure high quality, reliable IP across a wide range of foundries and process technologies. The company also prides itself on providing superior customer support and was named the 2006 Customer Service Leader of the Year in the Semiconductor IP Market by Frost & Sullivan. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit www.viragelogic.com.
|
Related News
- Freescale Selects Virage Logic's IPrima Mobile(TM) Ultra-Low-Power Memories and STAR Memory System(TM) for 65nm Chips Targeting Cell Phone Market
- Dolphin Integration strengthens their portfolio of Standard Cell libraries with the DUAL innovation targeting Low Power designs
- Virage Logic Introduces Ultra-Low-Power Semiconductor IP Platform, Allowing Up to 20X Reduction in Static, 80 Percent in Dynamic Power Dissipation
- Dolphin Integration announce the availability of new ROM TITAN and ultra low leakage standard cell library SESAME BIV at TSMC 55 nm LP eFlash
- Dolphin Integration widens their catalog with libraries targeting both Low Power and High Speed
Breaking News
- SiFive Empowers AI at Scale with RISC-V Innovation
- Arasan Announces immediate availability of its SPMI IP (System Power Management Interface)
- UPMEM selects Semidynamics RISC-V AI IP for Large Language Model Application
- Sondrel now shipping chips as part of a complete turnkey project
- Avant Technology Appointed as Sales Representative in Asia for EnSilica's eSi-Crypto IP
Most Popular
- Now Gelsinger is gone, what is Intel's Plan B?
- Synopsys Posts Financial Results for Fourth Quarter and Fiscal Year 2024
- Qualitas Semiconductor's MIPI D-PHY IP Powers Mass Production of Renesas AI MPU
- Marvell Unveils Industry's First 3nm 1.6 Tbps PAM4 Interconnect Platform to Scale Accelerated Infrastructure
- Alphawave IP - Announcement regarding leadership transition
E-mail This Article | Printer-Friendly Page |