Mark LaPedus, EE Times(04/27/2008 8:15 PM EDT) SAN JOSE, Calif.
— Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has unveiled a new and possibly controversial strategy that involves more collaboration in the early stages of the IC design process.
TSMC's program is aimed to reduce development cycles and manufacturing costs, according to analysts. But it could also possibly cause a major stir in the industry, as the silicon foundry giant wants more of the IC pie and appears to be encroaching on the turf in the third-party EDA, IP, packaging and test communities.
As part of its strategy, TSMC (Hsinchu, Taiwan) is quietly pushing a concept called the Open Innovation Platform (OIP), according to Gartner Inc. During its technology conference last week, TSMC also disclosed details about its roadmap in the chip-packaging front, including its internal efforts in the three-dimensional (3D) arena.
OIP is a program that involves more "collaboration between the foundry and its clients at the early stages of the design phase," said Jim Walker, an analyst with Gartner (Stamford, Conn.), in an e-mail newsletter.
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