Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Dolphin Integration announces a SESAME Library stem for ultra low power and low voltage in 0.18 um
The performance of of each islet of the SOC must be optimized differently for best effectiveness: for lowest dynamic power or for lowest leakage, with or without retention registers, etc. Dolphin Integration's low power and low voltage library SESAME uVSvHS enables operating as low as 0.9 V in 0.18 µm and is available in TSMC G, TSMC ULL and IBM process. Its association with an inductorless switching converter enabling a variety of voltage ranges can be embedded for better cost efficiency than with an external Power Management Unit.
About Dolphin Integration’s SESAME library
SESAME is a grouping of specialized and well-structured “library stems”: all such library stems are ultimately optimized for one prime criterion, e.g. Low Power Consumption (LC), High Density (HD), Low Leakage (LL), while simultaneously offering a good performance on a second criterion. SESAME is classified as a “Reduced Cell Stem Library” (RCSL): each library stem of SESAME results from a handcrafted work of art, cell by cell. Indeed, each cell is carefully optimized at both electrical and layout levels to provide the highest performance on the chosen optimization criterion of the stem.
More information on SESAME at:
http://www.dolphin.fr/flip/sesame/sesame_overview.html
|
Dolphin Semiconductor Hot IP
Related News
- Dolphin Integration announce the availability of new ROM TITAN and ultra low leakage standard cell library SESAME BIV at TSMC 55 nm LP eFlash
- MagnaChip to Offer Cost Competitive Compact Standard Cell Library for Low Power Applications
- Dolphin Integration strengthens their portfolio of Standard Cell libraries with the DUAL innovation targeting Low Power designs
- Dolphin Integration launches their SESAME library for High Voltage and Low Leakage in 0.18 µm
- 90% Reduction in power consumption for RFID chips with Dolphin Integration's SESAME eLC standard cell library
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |