Design VERIFYer 3.0 Increases Avant!'s Lead in Formal Equivalence Checking
FREMONT, Calif., March 6 -- Avant! Corporation (Nasdaq: AVNT), the leader in formal verification, today announced Design VERIFYer 3.0. This enhanced version of the market leading equivalence checker increases Avant!'s lead over the competition in the fast growing formal verification market.
With Avant!'s commitment and record for innovation, Design VERIFYer continues its history of technical leadership. While others are just announcing or developing their complete language support, Design VERIFYer has provided robust Verilog and VHDL native language and library support for years. Leading the formal verification market with over 56% market share (source: DataQuest) and the largest installed base, in 1999 Design VERIFYer saw its successful customer base grow more than 70% to well over 250 sites. This worldwide customer base with its widely varying design types and styles demonstrates the robustness and quality of Design VERIFYer.
``At Sitera, we have multiple Verilog models for most parts of our chips, including the cell libraries,'' said Steve Sheafor, executive vice president of Engineering and CTO at Sitera, Incorporated. ``We used Design VERIFYer to prove that all the libraries are equivalent, whether they be behavioral, structural, or based on primitives and UDPs.''
``We also routinely verify all netlist changes made during the layout process, including rebuffering, clock trees, and scan insertion,'' continued Sheafor. ``This lets us quickly detect whenever any of our supposedly 'correct by construction' methods get broken.''
Customers like Sitera have used Design VERIFYer to provide complete confidence that their equivalence checker produces correct results 100% of the time.
``As the demands of multi-million gate SoC and ASIC designs continue to increase, IC designers are faced with an unavoidable transition to a new generation of formal equivalence checking technology,'' said Gerald C. Hsu, president, chairman and CEO of Avant! Corporation. ``We are pleased to offer the next-generation Design VERIFYer 3.0, which advances our state-of-the-art technology in formal equivalence checking by achieving significant new capacity and speed, increasing performance, and enhancing ease-of-use.''
Avant! has significantly enhanced capacity and performance of Design VERIFYer providing up to a 100X performance improvement for handling multi- million gate SoC and ASIC designs. The Design VERIFYer 3.0 release introduces Optimized Algorithm Selection (OAS) technology, resulting in dramatic ease-of- use improvements and further increasing the capacity of Design VERIFYer's unique formal analysis algorithms. Additionally, Design VERIFYer 3.0 now includes support for re-timed circuits, and improved mapping technology.
Design VERIFYer is widely recognized for providing the most robust and accurate algorithms in equivalence checking. These algorithms are developed, refined and tested with over 22,000 customer-supplied design cases. Through the new OAS technology, algorithm choice is automatically optimized for the best performance, fastest completion and minimum memory usage, allowing Design VERIFYer to handle much larger designs. For example, a design of 3 million gates, which previously took 15 hours for an RTL to gate comparison, completed in just 40 minutes with OAS without customer intervention or input. Algorithm selection, done on a cone-by-cone basis, is automatic, thereby allowing customers to run Design VERIFYer ``out of the box'' with little or no setup, an important characteristic for the SoC and ASIC designer. Additional ease-of-use features include automatic master/slave compression and significantly improved mapping algorithms for both name-based and nameless mapping of state points.
Design VERIFYer 3.0 also introduces support for re-timed designs. Often a designer will change the gate-level netlist for increased performance or for sequential optimization. Such changes may include manual modifications or new synthesis resulting in modified or additional logic in the gate-level netlist. This logic doesn't exist in the RTL description, yet must be functionally identical to the golden RTL. In this situation, many equivalence checkers identify a mismatch between the RTL and the modified gate-level design, requiring the user to intervene and define state points for design comparison. Design VERIFYer 3.0 automatically recognizes these situations and correctly maps state points without user intervention.
Design VERIFYer 3.0 is in beta release and will begin production shipments in April. Design VERIFYer users with up-to-date maintenance contracts can request the new software and keys at no additional charge. The product will be demonstrated at HDLCon 2000 in San Jose on March 9-10.
Avant! (pronounced ah VAHN tee) Corporation develops, markets, and supports integrated circuit design automation (ICDA) software for the design of deep submicron ICs including microprocessors, microcontrollers, application-specific standard products (ASSPs) and complex application-specific integrated circuits (ASICs). Avant!'s product offering and chip design methodologies cover design authoring, process characterization, circuit simulation and analysis, HDL simulation, formal verification, floorplanning, physical design and VDSM optimization, interconnect parasitic extraction, timing simulation, physical verification, IC/package co-design and a full suite of technology computer-aided software for process simulation, device modeling and mask synthesis. Avant! also provides physical foundation IP libraries for integrated circuit design. Avant!'s tools support hierarchical design methodologies as well as incremental design changes in all phases, and they offer the capacity needed for multi-million-transistor devices.
The company is headquartered in Fremont, California, with sales offices worldwide. Telephone: 510-413-8000. Fax: 510-413-8080. Worldwide web: www.avanticorp.com.
NOTE: Avant! and Design VERIFYer are trademarks of Avant! Corporation. All other company and product names mentioned herein are trademarks or registered trademarks of their respective owners and should be treated as such.