Mentor Graphics and Tensilica Accelerate System-on-Chip Development And Verification From Months to Hours

IP News

Mentor Graphics and Tensilica Accelerate System-on-Chip Development And Verification From Months to Hours

WILSONVILLE, Ore., Feb. 28 -- Extending its market-leading, system-on-chip (SoC) co-verification environment to the surging configurable processor market, Mentor Graphics Corporation (Nasdaq: MENT) today announced it offers the first co-verification platform to model Tensilica's flagship Xtensa(TM) 32-bit configurable processor. The Mentor Graphics® Seamless® Co-Verification Environment (CVE) now allows cycle-accurate models of Xtensa-based processor variants to be developed and validated in less than one hour. The Xtensa processor, popular in communications and networking applications, is the first fully configurable core to be modeled within a co-verification environment.

``Seamless CVE is a critical success factor for accelerating time-to-market for Xtensa-based designs in applications such as networking and telecommunications,'' said Chris Rowen, president and chief executive officer for Tensilica. ``Prior to tape-out, customers can now make area, speed, power and code density adjustments on a virtual platform, avoiding unnecessary silicon re-spins. By allowing architectural exploration to be completed before silicon, designs can experience as much as fifty times improvement in the performance of key software algorithms, performance that can be translated into lower power, higher speed or increased functionality.''

Until now, accurate models for configurable processor variants typically took months to develop and validate. The Xtensa/Seamless CVE integration breaks through this bottleneck. The Xtensa Processor Generator from Tensilica allows users to both customize a processor's instruction-set, interrupts, memory, and peripherals, to suit application needs, and to generate cycle-accurate hardware/software processor support packages (PSPs) for the application in Seamless CVE, all in less than an hour. The PSPs are created and can then be instantly downloaded from the Tensilica web site. Immediate availability of the PSPs allow embedded system developers to optimize software and processor hardware to meet specific speed, power, and feature requirements. This rapid iteration loop, encompassing customization of the processor core and validation with the end product, allows designers to explore multiple architectures and make design trade-offs in a virtual prototype.

``Tensilica leads the development of configurable processors and this agreement endorses the importance of co-verification in re-configurable processor design environments,'' said Serge Leef, general manager of the system-on-chip verification business unit for Mentor Graphics. ``With the high degree of customization involved in the configurable processor market, developing cycle-accurate models has been a time-consuming process. Mentor Graphics and Tensilica have worked closely to support the Xtensa configurability, slashing the traditionally lengthy feedback loop and allowing design optimizations to be made instantly based on real-time data.''

About the Xtensa Core

The Xtensa 32-bit configurable processor allows embedded system designers to rapidly build differentiated, optimized and synthesizable processor cores for use in ASIC-based products. Designers can use the Xtensa Processor Generator to configure a processor; to concurrently create a complete GNU-based software development environment (compiler, assembler, linker, profiler, debugger); to create an instruction-set-simulator; and, to produce an RTOS overlay and to add designer-defined instructions uniquely developed for the target design. Each new instruction-set simulator that is automatically generated can be used by the Seamless Co-Verification Environment to model the new processor configuration, along with any new designer-defined instructions. The Xtensa processor features 16/24-bit RISC instruction set architecture, 320MHz (typical) performance, 0.7 sq. mm core area (base configuration) and 0.4mW/MHz power dissipation in 0.18um technology.

Availability

The Seamless CVE Processor Support Package (PSP) for the Xtensa configurable processor is available on the Sun Solaris platform. For more details on additional supported platforms, simulators and debuggers, and availability information on Seamless PSPs, visit its web site at http://www.mentor.com/seamless/psp_listings.html.

About Mentor Graphics Seamless CVE

Linking the best in embedded software development tools with logic simulation, Mentor Graphics' Seamless CVE is the market leader in hardware/software co-verification with a 62% market share as reported by Dataquest. Seamless CVE delivers high performance co-verification months before a hardware prototype can be built, allowing software and hardware development to be parallel activities, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.

About Tensilica

Tensilica(TM) was founded in July 1997 to address the fast-growing market for application-specific microprocessor cores and software development tools in high volume, embedded systems. Using the company's proprietary Xtensa(TM) Processor Generator, system-on-a-chip (SoC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company has over 70 engineers engaged in research, development, and customer support from its offices in Santa Clara, California, Waltham, Massachusetts, and Yokohama, Japan.

Tensilica is headquartered in Santa Clara, California 95054 at 3255-6 Scott Boulevard, and can be reached at 408-986-8000 or via www.tensilica.com on the World Wide Web.

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $500 million and employs approximately 2,700 people worldwide. Company headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.

NOTE: Mentor Graphics and Seamless are registered trademarks. Co-Verification Environment, and CVE are trademarks of Mentor Graphics. Xtensa is a trademark of Tensilica. All other company or product names are the registered trademarks or trademarks of their respective owners.

CONTACT: Anne Cirkel, Marketing Communications of Mentor Graphics Corporation, 503-685-7934, or anne_cirkel@mentor.com; or Jeremiah Glodoveza of Benjamin Group/BSMG Worldwide, 408-559-6090, or jeremiah@benjamingroup.com, for Mentor Graphics Corporation.