May 19, 2008 -- Algotronix Ltd., a supplier of cryptographic intellectual property, announced that its unique DesignTag thermal active tagging system for identifying design intellectual property will be released to customers on 26th May. A technical paper on the technology will be presented at the Hardware Oriented Security and Trust workshop which is co-located with DAC.
DesignTag consists of a small, low power, IP core which is added to the design to be protected and DesignTag reader software and data logging hardware which can sense the tag through the chip package. Each DesignTag IP core has a unique identification code which can be used to look up details of the protected product in a database. The DesignTag IP core is a purely digital circuit which works by creating minute temperature changes which are then detected using a low cost thermocouple placed in contact with the chip package. The DesignTag reader software accesses a database of tag information and based on this demodulates the spread spectrum thermal signal transmitted by the tag and determines which tag is inside the chip. It then provides design information corresponding to that tag. Customers can decide whether to make their tag information available in the public database so that all users of the DesignTag reader can detect their tags or whether to keep their tags private for internal use only.
The first application area to be addressed is identifying the bitstream configured into FPGA chips; future products will address identifying intellectual property cores within SoC chips and detecting ‘fake’ integrated circuits in the supply chain where the package markings do not correctly identify the chip within. FPGA users are a natural market for DesignTag since the ink markings on an FPGA chip identify the FPGA manufacturer and model, not the user design configured into it.
In a typical application the DesignTag will consume around 5mW when active and will only be enabled for around 15 minutes after the protected chip is powered on. The energy costs are therefore negligible in most cases. The tag also requires very low silicon resources – around 200 slices on a Xilinx Spartan 3. Introductory pricing to use the DesignTag IP core in one FPGA design is £100 ($200) and the DesignTag reader software is priced at £400 ($800). Products and pricing to use DesignTag on ASIC and ASSP chips will be announced at a later date. The FPGA products are available from Algotronix’ web store at
www.design-tag.com . A data-logger such as the Pico Technology TC08 is also required to collect the temperature samples from the tagged chip.
DesignTag has the ability to transmit status codes under the control of the user’s design – for example if the user design detects a fault condition it could instruct DesignTag to transmit a different code than it would use during normal operation. This can be a useful way of communicating fault information for diagnostic purposes in an embedded system where there is no other fault reporting mechanism.
Tom Kean, Managing Director of Algotronix commented, “Unlike simple ink markings on the chip package DesignTag is accessible to FPGA designers, CAD companies and IP core vendors and is secured against falsification. In an environment where blatant copies of all types of electronic equipment from cellular phones to complex medical electronics are being offered tagging an FPGA bitstream before letting it out of the building is simple common sense.â€
About Algotronix Based in Edinburgh, Scotland Algotronix develops and licences a range of encryption and design security intellectual property to customers throughout the world.
See:
www.algotronix.com
