Free 32-bit processor core hits the Net
By Peter Clarke, EE Times
February 28, 2000 (10:52 a.m. EST)
LONDON A loose-knit organization called OpenCores is offering a free 32-bit processor intellectual-property (IP) core in a move that could undermine such commercial IP licensors as ARM and MIPS.
Before the end of this month, engineers should be able to download VHDL description files and documentation for the OpenRISC 1000 core over the Internet at no charge. Engineers can already download a C language compiler free.
The engineers should then be able to work with the core, add to it, synthesize it for FPGA or ASIC implementation, and build a whole product line around it all at no cost.
The one catch is that the OpenRISC 1000 comes with minimal support. So if engineers can't get the core to work, or if it is not all it's claimed to be, they are largely on their own.
Nonetheless, analysts say the offering, and others like it, may eventually alter the semiconductor IP landscape as radically as Linux has transformed the operat ing-systems market.
The move has raised warning flags at IP companies. According to the OpenCores organization, ARM Ltd. (Cambridge, England), the leading licensor of processor cores, has already warned the group not to build clones of any of its cores. Nevertheless, the OpenCores organization said it is working on an OpenRISC version that executes the MIPS-I instruction set of MIPS Technologies Inc. (Mountain View, Calif.), an ARM rival.
OpenRISC 1000, which is not a clone and executes its own set of instructions, is due to be available from the OpenCores Web site in a matter of days. That site is one of many such sites sprouting from a fertile hobbyist and academic non-commercial ethos that would make hardware IP cores available free. Other such sites include those of OpenIP and the Free-IP Project.
The approach is similar to the practice among amateur programmers of making software utilities and games available free over the Internet.
The OpenCores Web site says that the VHDL source code for the OpenRISC 1000 CPU core and a combined MMU and cache will be available this month.
Damjan Lampret, a 22-year-old computer science student at the University of Ljubljana, Slovenia, is one of the forces behind www.opencores.org and a designer of the OpenRISC architecture. "We are modeling ourselves on the Free Software Foundation. We're trying to work in a similar way," he said, speaking over the telephone from Ljubljana.
"We're not a legal entity; it's more like a club. But people are starting to work together, and some designs are already done."
The design elements come from students, hobbyists and professional engineers who communicate by e-mail and instant messaging and who so metimes don't even know in what countries their correspondents and collaborators live. For them, the e-mail address or ICQ number of a collaborator is all-important and the collaborator's physical location irrelevant.
In the last two months of 1999, Lampret and his co-workers designed the 32-bit microprocessor architecture that they call OpenRISC 1000, or OR1K. Lampret also ported the GNU C-compiler to the OpenRISC architecture and is making them both available on the Internet. An OpenRISC prototyping board comprises a Xilinx FPGA and Xilinx programmable-logic device.
"OR1K is small and quite fast. It occupies about 70 percent of the smallest Xilinx Virtex gate array, which they label as 50k gates, and runs at about 100 MHz," said Lampret.
The design first ran compiled C code on the prototype board late on Dec. 31, he said, communicating some of the excitement he felt at the time. "Exactly before midnight on New Year's night, OR1K executed its first instructions actually, several millions of them."
Lampret said the initial goal had been to publish the core in 1999 and to port the Linux operating system to it, but preparation for his university exams set back that schedule. Further, the documentation effort has lagged development of the OpenRISC design.
"The design is more or less complete, but I am working to make it more generic. There are some aspects of the design that are Virtex-dependent that need to be replaced," he said.
The starting premise for the work was a single-issue minimal RISC implementation that would come close to executing one instruction per cycle and that would be good for embedded applications.
"I studied most of the RISC architectures that exist today and developed my own list of the most common and useful instructions. It's closest to the DLX or early MIPS architecture. It's a very basic 32-bit RISC with a load-store architecture and no floating-point capability at the moment," Lampret said. (The DLX processor is a RISC machi ne described by the pioneers of RISC, John Hennessy and David Patterson, in their book Computer Architecture: A Quantitative Approach (Morgan Kaufmann Publishers Inc.).
Lampret said he has settled on a mixed 16- and 32-bit instruction format. Although he has not pursued 16-bit format instructions or 16-to-32-bit instruction format translation (used in ARM's Thumb and considered good for embedded applications because it improves code density), Lampret said OpenRISC code is still compact compared with that of many other processors.
"I compiled the same code for X86, Sparc, MIPS and Alpha, and they were all bigger compiled programs," he said.
The register file architecture is similar to that of the Sparc, Lampret said. "It makes sense to have register windows. At the moment we have thirty-two, 32-bit registers, but that could change with different implementations."
Lampret said he had no hardware performance benchmarks yet but that software simulation of the Dhrystone benchmark showed the OpenRISC 1000 achieving 100 Mips at 100 MHz.
Jim Tully, EDA analyst with Gartner Group's Dataquest subsidiary in Egham, England, said, "Who's to say that this couldn't evolve into something the industry could use? Before Linux came along, who would have said that [the Linux phenomenon] could happen?" Tully said, "People will be paranoid about [OpenRISC's] background, its provenance, its quality. On the face of it no one would want to look at it, but no doubt people will download free cores and try them out in low-risk situations. If OpenRISC works, it could migrate up."
Tully observed that Sun Microsystems had done something similar with community source licensing of its Sparc architecture, although Sun requires users to pay unit royalties when chips including the Sparc are manufactured, so it is not a free processor.
Need for control
But Tully warned that for any processor architecture to be successful, some central control of the compatibility of different versions is needed and that requires administrative and legal effort.
While Lampret's and OpenCore's philosophy is that the OpenRISC should be available for anybody to download, Lampret is finding it is impossible to avoid legal complications.
"If we are going to have a community license, along the lines of Linux, [users] must return any changes or enhancements to us, but we have not yet decided on that," he said. "We may have a GPL license, a general public license as defined by the Free Software Foundation."
Why would a student, or anyone else, design a useful and therefore potentially valuable IP core and then give it away? "Many reasons," said Lampret. "Although I am still a student, I have worked for many companies. Once I get another job, I will be too occupied to do much on OpenRISC.
"Also, I would like to work in Silicon Valley, and to get a job there you need good references. The best reference is to show your work, but it is often not possible to bring work from a previous employer. OpenRISC should be a good reference."
The trend among students and hobbyists to field free cores doesn't seem to have the established commercial IP and chip vendors running scared, but it does have them restating their legal positions.
Lampret said OpenCores had considered designing a clone of one of the ARM RISC cores, essentially taking the list of instructions that an ARM core executes and building a machine that could do the same and therefore would be able to run compiled ARM code.
"We contacted ARM [about the possibility], but their response was, 'You'd better not do that.' Can they do that?" Lampret asked.
At ARM Ltd., Pete Magowan, vice president of worldwide sales, said the company takes "the protection of our intellectual property very seriously but can't comment on specific cases. We prefer an open partnership model that broadens access to ARM architectures."
Lampret is still refining OpenRISC and has a superscala r version of the core, dubbed OpenRISC 1002, that's optimized for speed. The dual-issue OpenRISC should operate at 170 MHz in a Xilinx XCV-E FPGA and offer about 250 Mips of performance, Lampret said.
He further claims to have a 'lite' version, the OpenRISC 1001, optimized for gate count that runs at 80 MHz in a Xilinx Virtex XCV50 and that provides 80 Mips of performance. The core can be adapted to run MIPS-I code, Lampret said.
"You can replace the decoder module and some minor parts of OR1K with a set that is designed for MIPS-I [instructions], synthesize it and then execute MIPS-I code," Lampret explained via e-mail. "I don't know what MIPS will say about this. Perhaps ARM will be next."
MIPS Technologies declined to comment on a core about which it claims to know very little. Last year, however, MIPS sued Lexra Inc. (Waltham, Mass.), a designer of MIPS-like cores, alleging patent infringement. Lexra countersued, asserting that it does not infringe MIPS' patents and requesting that the patents referred to in the MIPS suit, filed Oct. 28, 1999, be declared invalid. It also seeks legal remedies against MIPS for interference with Lexra's business relations.