Globetech Solutions' Verification IP for Latest IEEE Test and Debug Standard Selected by STMicroelectronics
The VIP verifies design blocks conforming to any of the six compliance levels defined by the IEEE standard, significantly reducing time to functional closure and increasing the quality of first silicon. The metric-driven compliance management suite accurately assesses the interoperability of IEEE P1149.7 IP in system topologies prior to integration. The solution supports complete reuse of block-level environments in chip-level verification flows of IEEE P1149.7-enabled systems.
“As an early adopter of the IEEE P1149.7 standard, ST collaborated very closely with Globetech on the development and validation of our design IP and their VIP,” said François Oswald, Digital Design Director, Wireless Multimedia Division, STMicroelectronics. “Globetech's high quality products, outstanding support and on-time deliverables have made a major contribution to the success of our IEEE P1149.7 IP development.”
Originally proposed by the Mobile Industry Processor Interface (MIPI) Alliance, IEEE P1149.7 extends IEEE 1149.1™ to support the needs of debug applications for products with complex digital circuitry, embedded software, and one or more CPUs. The standard addresses key challenges such as enhanced functionality for test access, reduced pin-count and improved power management.
“Any integrated circuit using the IEEE 1149.1 interface may use this standard to reduce the test interface pin count from four or more to two, while at the same time providing more advanced capabilities,” said Rob Oshana, chairman of the IEEE P1149.7 working group. “Because of its advanced capabilities it's important to have a verification and compliance infrastructure in place to support it. Globetech worked closely with the working group to help identify implementation challenges in advance, leading to a more robust specification.”
Verification for Test
The IEEE P1149.7 VIP and compliance management system extends Globetech's Verification for Test (VFT™) product suite, which includes verification automation capabilities for test and debug standards such as JTAG, IEEE 1500™ and the IEEE 1450™ family.
“Getting test and debug functionality right the first time is critical for multi-processor, multi-core SoC and SiP because it provides the foundation for post-silicon validation,” said Stylianos Diamantidis, Managing Director of Globetech Solutions. “Supporting a complex specification such as IEEE P1149.7 in our VFT product line gives our customers the tools and methodology they need to meet this requirement.”
About Globetech Solutions
Globetech Solutions provides verification intellectual property products and electronic design automation solutions. Globetech addresses key challenges in electronic system level design from specification to volume production and field support. Customers, including some of the world's largest IDMs, design IP suppliers and systems manufacturers, use Globetech's products and services to increase quality, control predictability, and improve productivity. For further information, please visit www.globetechsolutions.com.
|
Globetech Solutions Hot Verification IP
Related News
- Synopsys Announces Industry's First Verification IP and Test Suites for Latest MIPI CSI-2 v2.0 and PHY Specifications
- IPextreme and Texas Instruments Host Webinar on "cJTAG – IEEE 1149.7: Next Generation Test and Debug"
- Denali's Industry-Standard PureSpec Verification IP Utilized by IBM for Latest CoreConnect Bus Architecture Toolkits for SoC designs
- Allegro's MPEG-4 AVC/H.264 Certification Test Suites Selected by STMicroelectronics
- VESA Launches Industry's First Open Standard and Logo Program for PC Monitor and Laptop Display Variable Refresh Rate Performance for Gaming and Media Playback
Breaking News
- Sondrel appoints Gareth Jones as VP ASIC
- Accenture Completes Acquisition of XtremeEDA to Expand Silicon Design Capabilities in Canada and US
- Xiphera's first financing round successfully completed
- Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies
- 2022 a Focus for 12-inch Capacity Expansion, 20% Annual Growth Expected in Mature Process Capacity, Says TrendForce
Most Popular
- Weebit Nano tapes out ReRAM demo chip to SkyWater foundry
- Intel Foundry Services Forms Alliance to Enable Design in the Cloud
- Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture
- Synopsys and Arm Strengthen Partnership to Advance Next-Gen Mobile SoCs for Arm's Total Compute Solutions
- SiFive Expands Global Operations, Opens UK R&D Center in Cambridge
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |