HDL Design House has a new representative for Western Europe
SoCVerify Kit consists of competitively priced verification IP that cover a large number of standards and protocols such as: I2C, HyperTransport, Serial RapidIO, SATA, ATA/ATAPI, SAS, LPC, PCI, PCI-X, SPI4, SMBUS, and PMBUS. It supports verification methodologies eRM, URM and OVM. SoCVerify Kit offers a multi-language verification IP environment and a smooth transition to advanced verification methodologies.
HDL Design House UVCs Available for EEP | |||||
I2C* | SATA** | PCI-X** | Serial Rapid IO | HyperTransport | SM/PMBUS** |
SPI-4 | SAS | JTAG** | Compact Flash | ATA/ATAPI** | LPC** |
* OVM Ready UVC ** SV interface available
About EDA4YOU:
EDA4YOU is Sales Representative organization located in Germany/Europe and focused to assist in marketing & sales of products needed for electronic design such as ASIC-Prototyping, Design-Services, EDA-Software related to IC- and PCB-Design, IP-Cores.
About HDL Design House:
HDL Design House specializes in rendering design and verification services for SoC projects and providing soft IP cores and verification IP (VIP) based on advanced verification methodologies such as OVM and URM. With primary focus on fulfilling each customer's unique requirements, HDL Design House can offer design and verification services for SoC projects. In order to meet requirements of the most complex projects, HDL Design House creates dedicated engineering teams who also provide support and maintenance for VIP. The company's high-quality and verification IP (VIP) can be easily integrated to rapidly create sophisticated verification environments for complex SoCs. The VIP program is built around advanced verification methodologies (OVM, URM) and languages (System Verilog, e). HDL Design House delivers high quality VIP with rigorous QC procedures and helps customers develop their projects by combining design and verification services and VIP library, called SoCVerify Kit, with unified organization, implementation and supported verification methodologies. Further more, all verification IP from SoCVerify Kit can be used and evaluated with HDL Design House Extended Evaluation Program (EEP). This program allows eligible customers to evaluate VIP from SoCVerify Kit for three months at no charge. The company also delivers component (VITAL) models for major SoC product developers. Having developed more than 400 VHDL VITAL models for major memory provider companies, HDL Design House has established a reputation as a market leader in VHDL/Verilog/System Verilog modeling. For additional information, please visit www.hdl-dh.com.
|
Related News
- HDL Design House Adds New Representative in Europe
- HDL Design House Appoints New Representative for Central Europe, Nordic Region and the US
- Capgemini boosts its semiconductor capabilities in Europe with acquisition of HDL Design House
- HDL Design House Appoints New Sales Representative for US and Canada
- HDL Design House and Mentor Workshop at Aviation Electronics Europe 2018
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |