CPF-Based 65nm Low-Power Reference Design Flow Address Complex Design Issues and Accelerates High-Performance, Low-Power Designs
DESIGN AUTOMATION CONFERENCE, Anaheim, Calif. - June 9, 2008 - Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and UMC (NYSE: UMC, TSE: 2303), a leading global semiconductor foundry, today announced the availability of a Common Power Format (CPF)-based low-power reference design flow targeted to the UMC 65-nanometer process. This reference flow enables customers to achieve optimal 65-nanometer low-power designs when used with UMC's Low Power Kit, which includes CPF-enabled libraries and other intellectual property.
This 65-nanometer low-power reference design flow uses UMC's "Leon" test chip as the reference design. Leon is an open source 32-bit RISC microprocessor core with other complex elements including SRAM. The Leon chip was partitioned into multiple voltage domains using the Cadence Low-Power Solution for design, verification, implementation and analysis. As proven with the Leon test chip, the combination of the 65-nanometer reference design flow and the UMC Low Power Kit enables increased productivity while managing design complexity, shortening time-to-market and reducing manufacturing risk.
The UMC 65-nanometer low-power reference design flow highlights key capabilities of the Cadence Low-Power Solution, including Cadence Incisive Unified Simulator for gate-level low-power simulation; Cadence Encounter RTL Compiler for synthesis, low-power and DFT cell insertion; Encounter Conformal Low Power for equivalence checking and low power design implementation checking; Encounter Test for ATPG; SoC Encounter RTL-to-GDSII system for floorplanning, powerplan and place-and-route; Encounter Timing System for timing and SI signoff; Cadence QRC Extraction; VoltageStorm Power Encounter for static power and IR analysis; and VoltageStorm Dynamic Gate and Virtuoso UltraSim for dynamic analysis of current surge at power up. In addition, UMC's Low Power Kit, including its CPF-enabled library, was validated as part of the reference design flow development.
"We are working closely with Cadence to address complex design issues that face designers at 65 nanometers, while enabling faster time to volume through an integrated low-power solution," said Darsun Tsien, UMC's vice president of design methodology. "Through our ongoing collaboration with Cadence, we are able to provide designers with validated low-power technologies to manage power concerns and meet aggressive time-to-market goals:"
"This CPF-based flow, the result of a joint effort between Cadence and UMC, accelerates implementation of low-power designs," said Chi-Ping Hsu, corporate vice president of IC Digital and Power Forward at Cadence. "The combination of UMC process technology and the Cadence Low-Power Solution provides our mutual customers with the ability to realize their aggressive project goals while preserving low-power intent throughout the design process."
This reference flow package includes design resources, implementation scripts, an application note and a comprehensive workbook. This 65-nanometer Low Power reference design flow is slated for availability in July 2008 through UMC sales.
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced system-on-chip (SoC) designs for applications spanning every major sector of the IC industry. UMC's SoC Solution Foundry strategy is based on the strength of the company's advanced technologies, which include production proven 90nm, 65nm, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 13,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com