NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
Dolphin Integration launches their SESAME library for High Voltage and Low Leakage in 0.18 µm
SESAME uHVuLL is the solution to these needs as it enables a leakage reduction by a ratio of 1000, while offering the capability to operate between 1.6 V to 3.6 V!
For more information on this state-of-the-art product, click here.
A free “Evaluation Tutorial” is provided with each evaluation kit for a smooth and fast discovery.
About Dolphin Integration’s SESAME library
SESAME is a grouping of specialized and well-structured “library stems”: each of them library is ultimately optimized for one prime criterion, namely Low Power Consumption (LC), High Density (HD), Low Leakage (LL), while simultaneously offering a good performance on a second criterion.
SESAME is classified as a “Reduced Cell Stem Library” (RCSL): each library stem results from a handcrafted design, with a unique advantage. Indeed, each cell is carefully optimized at both electrical and layout levels not only to provide the highest performance on the chosen optimization criterion of the stem, but also to enable the composition of stems, for an optimization with constraint, e.g. high density but with tight timing constraints.
More information on SESAME at: http://www.dolphin.fr/sesame
|
Dolphin Semiconductor Hot IP
Related News
- Dolphin Integration announces a SESAME Library stem for ultra low power and low voltage in 0.18 um
- Dolphin Integration announce the availability of new ROM TITAN and ultra low leakage standard cell library SESAME BIV at TSMC 55 nm LP eFlash
- Ultra high density standard cell library SESAME uHD-BTF to enrich Dolphin Integration's panoply at TSMC 90 nm eF and uLL
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
- Dolphin Integration announces a new generation of ultra-dense standard cell library for GSMC 0.18 mm uLL eFlash process
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |