Analyst: Cadence/Mentor merger "a bad idea"
(06/17/2008 2:54 PM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=208700171
SAN JOSE, Calif. — Cadence Design Systems is under pressure and may lose its top spot in the electronic design automation sector, but its proposed $1.6 billion merger with Mentor Graphics is "a really bad idea," said a veteran EDA analyst.
"You would be sticking together two companies that have little synergy, lots of overlap and enough combined debt with the deal to make it hard to keep the pace in R&D," said Gary Smith, principal of Gary Smith EDA (Santa Clara, Calif.). "This deal would be like tying a boat anchor to the two companies and potentially sinking them both," he added.
E-mail This Article | Printer-Friendly Page |
Related News
- Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation "Hercules" CPU
- Cadence Achieves TUV SUD's First Comprehensive "Fit for Purpose - TCL1" Certification in Support of Automotive ISO 26262 Standard
- Synopsys Extends Verification FastForward Program, Enabling Cadence Incisive and Mentor Graphics Questa Users to Adopt VCS Simulation with Fine-Grained Parallelism Technology
- Mentor's CEO on Merger Mania
- Cadence, Mentor Graphics and Breker Announce Collaborative Technology Contribution to Accellera Portable Stimulus Working Group
Breaking News
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results