NURNBERG, Germany -- During an embedded systems conference here today, Fujitsu Microelectronics Europe demonstrated the first implementation of a processor core in a new series of very-long instruction word (VLIW) designs. The FR-V series was announced last summer, and now it is a reality, according to Fujitsu Ltd.'s European chip operation.
The first core being released is the FR500, which executes four instructions simultaneously. The VLIW core consists of 32-bit integer instruction sets, and floating point and media instruction sets. Fujitsu said these functions amount to six execution units in the FR500 core (two integer execution units, two floating-point execution units, and two media execution units).
The FR500 core is aimed at multimedia applications, such as car navigation systems, digital TVs, and other products needing parallel execution of graphics and sound processing, said Fujitsu.
Fujitsu said its FR-V architecture has be en developed to offer system-on-chip (SoC) designers with a varied set of configuration options, said the company. A smaller, low-power FR300 core is now scheduled to be released by the end of 2000. Fujitsu said this RISC core will be marketed for mobile telephone applications.
The RR500 core has been designed for 0.18-micron process technology. Fujitsu said the first device to use the core is the MB93501, which operates at a frequency of 266 MHz, with a peak integer performance of 1,064 million instructions per second. It also performs 4,256 million operations per second for application processing and 1,064 million floating point operations per second.
The 7-by-7 mm MB93501 chip is packaged in a 352-I/O ball grid array (BGA). Its processor core has a power consumption of 1 watt, according to Fujitsu.