Veriest Verification (Israel) announces close collaboration with HDL Design House (Serbia)
June 24, 2008 -- Veriest Verification, industry leader in verification methodologies, planning and execution, and HDL Design House, specialized in building dedicated teams to deliver complete design and verification services and creating reusable IP cores and verification components, decided to collaborate closely on delivering design and verification services to the Israeli market.
“We've found HDL Design House to be a highly professional VLSI design and verification services company, capable of executing large scale projects on time,” said Hagai Arbel, CEO of Veriest Verification. “ HDL Design House has excellent facilities, IT security and project management tools and its engineers are highly motivated experts with many years of experience. It also has a wide selection of proven, top-notch Verilog and Verification IP supporting different verification methodologies.”
Hagai Arbel added: “Collaboration with HDL will take Veriest's services to Israeli semiconductor market a step forward. Together both companies will deliver a wider range of cost effective solution for today's VLSI challenges.”
“HDL Design House is interested in expanding its business on the Israeli market. We are looking forward to close cooperation with Veriest Verification. HDL Design House and Veriest Verification technical teams will work together on project execution, bringing unique value for Israeli customers. This synergy will provide a special benefit for the customers in Israel as this model combines off-shoring (HDL Design House) with local and direct technical management (Veriest Verification) in a complementary way,” said Predrag Markovic, CEO and President of HDL Design House.
About HDL Design House
HDL Design House specializes in rendering design and verification services for SoC projects and providing soft IP cores and verification IP (VIP) based on advanced verification methodologies such as OVM and URM. With primary focus on fulfilling each customer's unique requirements, HDL Design House can offer design and verification services for SoC projects. In order to meet requirements of the most complex projects, HDL Design House creates dedicated engineering teams who also provide support and maintenance for VIP. The company's high-quality and verification IP (VIP) can be easily integrated to rapidly create sophisticated verification environments for complex SoCs. The VIP program is built around advanced verification methodologies (OVM, URM) and languages (System Verilog, e). HDL Design House delivers high quality VIP with rigorous QC procedures and helps customers develop their projects by combining design and verification services and VIP portfolio. The company also delivers component (VITAL) models for major SoC product developers. Having developed more than 400 VHDL VITAL models for major memory provider companies, HDL Design House has established a reputation as a market leader in VHDL/Verilog/System Verilog modeling. For additional information, please visit www.hdl-dh.com.
About Veriest Verification
Veriest Verification is a select team of VLSI design and verification specialists. Applying our extensive knowledge, we cross the toughest VLSI hurdles and provide top-quality closure design and verification solutions.
Veriest consists of verification methodologists, program managers, designers and developers. Our teams provide complete project coverage, supporting it from the Arch Spec phase through development to production, establishing completeness against the plan. We ensure the best project results by adhering to a consistent methodology, devised together with the client at the onset of the project. For additional information, please visit www.veriest-v.com
|
Related News
- HDL Design House has opened New design center in Niš - Serbia
- HDL Design House Webinar: Reducing Integration and Verification Effort in SoC Design
- Design Verification Challenges in Modern SoCs - HDL Design House Webinar
- HDL Design House New Verification Seminar in Switzerland: Maximizing Verification Efficiency
- HDL Design House New Verification Seminar in Austin: Maximizing Verification Efficiency
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |