New platform shortens SoC development times and delivers cost/performance-optimised solutions
July 29, 2008 -- Toshiba Electronics Europe (TEE) has announced a new system-on-chip (SoC) design and verification platform that will significantly shorten ASIC and ASSP development time. The CPS (Chip-Package-System) codesign/ co-verification platform supports the rapid identification of the optimum SoC package as well as delivering the cost/performance benefits and improving verification accuracy prior to hardware prototyping.
Based on collaborative and simultaneous development of the chip, the package and the PCB system board, Toshiba’s CPS allows designers to take an overall system view and perform a number of traditionally sequential and isolated tasks in parallel. Specifically, CPS allows IC designers to create a detailed virtual package substrate while the chip development is still in progress and before the designing of the physical package substrate begins. From the package substrate model the designer can then extract an accurate SPICE model. By combining this SPICE model with the chip I/O model and a PCB model signal integrity and timing verification on the chip-package-system design can begin before the detailed chip design is completed.
The CPS platform includes Toshiba’s proprietary chip planner, a virtual package design tool chain that provides for signal integrity (SI), power integrity (PI), thermal integrity (TI), IR drop and ESD analysis. Using the planner, designers can automatically perform SI, PI and TI checks early in the design cycle as soon as pin assignment and design information becomes available. This helps to reduce final costs by ensuring an optimum pin count at an early stage of the development. Die pad allocations and feasibility of initial package specification can also be validated.
A seamless interface within Toshiba’s CSP suite of tools enables rapid validation and ensures a smooth migration from virtual to real package. Toshiba file formats are adapted to open EDA vendor formats, completely eliminating the need for manual work in the design chain. The new platform is fully supported by the engineering teams at Toshiba’s European LSI Design and Engineering Centre (ELDEC) in Düsseldorf. Target applications will be those where high data rates and smaller process geometries require ever more complex and higher performance implementations. These include multi Gbps SerDes designs, DDR interfaces, precise analogue I/Os, PCI Express and SATA implementations, USB 2.0 high-speed PHYs and wide data path applications using 32-, 64- and 128- bit bus architectures.
For more information on Toshiba’s ASIC and Foundry business, please visit www.toshiba-components.com/ASIC.