Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)
A significant decrease in the number of gates does not affect performance, which surpasses the original MCU by more than 4 times. Gliwice & Bielsko-Biala, Poland, July 31st, 2008
– The silicon Intellectual Property (IP) provider, Evatronix SA, announced today the T8051
IP Core - the world’s smallest microcontroller that implements Intel™ 8051 Instruction Set Architecture. Thanks to this considerable size reduction and efficient management of available resources the design has one of the best performance-to-size ratios on the market.
With its 2700 gates, the T8051 is addressed to IC designers who want to retain complete 8-bit architecture functionality while substantially reducing the size of their systems. Engineers working with mixed signal designs, where the space is still a significant factor, will like the idea of replacing hard-coded control FSM with a programmable microcontroller, which was not possible with a significant difference in gate count between the two solutions. Now that the T8051 raises the bar for the minimal implementation size of this famous microcontroller’s architecture, its versatility and ability for configuration make it an obvious choice.
T8051 has more advantages over the industry standard 8051 than the size alone. Instruction cycle latency has been tuned to minimize hardware resources, however, the core still performs 4.1 times better than the original Intel™ 8051 in terms of Dhrystone MIPS per MHz. Communication with both built-in and external memories has been accelerated by de-multiplexing the address and data buses, while alternate port functions such as external interrupts and serial interface are available on separate pins – all this to give the user a possibility to connect and effectively manage a greater number of peripheral devices.
T8051 also features a complete Evatronix Application-debugging Support Environment that enables users to control the microcontroller directly in target applications. It consists of the Evatronix Debug Interface, which is a software plug-in for Keil™ development environment, Evatronix Debug Pod for an easy IP Core-to-PC connection via the USB port and a built-in On-Chip Debug Support (OCDS) module implemented directly in the core itself. However, the OCDS can be removed for the final implementation to fit the T8051 into yet smaller space.
“The feedback we received from over 100 companies that licensed our 8051-compliant IP cores to design more than 200 chips showed there us a niche for an ultra-small, yet configurable version of this microcontroller, ” said Wojciech Sakowski, Evatronix President.“Many companies have been able to design an 8051-compliant IP, but achieving this goal with such a low number of gates and more than quadruple performance gain over the original Intel™ device gives us a significant competitive advantage. We believe our customers will find this combination particularly beneficial for a large class of their designs.” Availability and customization options
T8051 IP core is available for licensing now. Standard deliverables include various sets of scripts for trouble-free synthesis and simulation as well as an extensive Verilog 2001 test bench, while the proprietary prototyping environment can be purchased as an option. Evatronix design team is ready to share its extensive expertise in developing this highly successful IP cores family and assist customers in adapting the microcontroller to their particular applications.