AMI rolls out PCI cores, Galileo takes MoSys license
By Michael Santarini, EE Times
January 18, 2000 (11:43 a.m. EST)
American Microsystems Inc. (AMI) has introduced two 32-bit PCI cores for its 0.35-micron XLArray and standard-cell families and announced plans for a 64-bit version to be released early this year. AMI said the technology lets companies convert Xilinx FPGA designs with PCI requirements to cost-effective AMI ASICs.
The company claims to be the only one currently offering a Xilinx-compatible ASIC PCI core.
This ASIC drop-in replacement is said to support all the functionality of the Xilinx proprietary core, including PCI Local Bus Specification Revision 2.2. AMI says all the configuration capabilities of the Xilinx FPGA core have been retained, eliminating the need for design adjustments when converting a Xilinx FPGA to an AMI ASIC. Designers can use the core to reduce costs while retaining the flexibility and functionality of the FPGA design, AMI said.
The AMI 32-bit/33-MHz and 64-bit/66-MHz ASIC PCI cores give users the same thre e configurable base address registers provided with the Xilinx core. In addition, the ASIC PCI cores have three more base address registers (for a total of six) and an expansion ROM base address register.
AMI also released a full-featured 32-bit/33-MHz Deluxe PCI core version that includes a complete set of command and status registers and a programmable interrupt structure that is said to simplify the connection of an embedded microcontroller to the Deluxe PCI core's user interface. The Deluxe core can be used with AMI's 0.35-micron XLArray and standard-cell families for ASIC design, or as an enhanced replacement for less complex FPGA PCI cores, such as the Xilinx core. The Deluxe PCI core also complies with PCI Local Bus Specification Revision 2.2.
The Xilinx-compatible and Deluxe full-featured 32-bit/33-MHz PCI cores are available now for FPGA-to-ASIC conversions and general ASIC development. Visit www.amis.com.
Galileo Technology I nc. has licensed MoSys Inc.'s 1T-SRAM for use on Galileo's Ethernet switches and other system-on-chip (SoC) products requiring high-performance memory. According to the companies, Galileo's products address the need for high-performance, highly integrated data communications ICs. By integrating 1T-SRAM in its recently announced GT-48350 and GT-48360 switches, Galileo says it has eliminated the need to use external memory devices when designing with these controllers.
With 1T-SRAM as the on-chip memory, the devices will offer more than twice as much memory and lower cost per port than other solutions, the two companies claim.
The exploding bandwidth requirements of the high-growth data communications market are driving the demand for high-performance, ultradense SRAM. The 1T-SRAM, capable of delivering the true random-access cycle times characteristic of SRAMs but at improved densities, is suited for the next generation of products in datacom markets, the companies said. Visit www.mosys.com and www.galileotechnology.com.