IRVINE, Calif. Broadcom Corp., a leading communications IC supplier, is among the first announced licensors of LSI Logic Corp.'s ZSP400 digital signal processing core.
LSI Logic said its superscalar dual-multiply-accumulate DSP architecture, with a 200-MHz clock, is capable of 800 Mips and 400 million multiply-accumulate operations. Since the DSP World Conference in November, LSI Logic has promoted the ZSP400 core as tradable intellectual property.
The Broadcom license underscores LSI's strategy of pitching the ZSP400 as an open architecture, in the same way that the ARM and MIPS microprocessor cores are seen as open standards, said Steve Williams, senior manager for DSP business development at LSI Logic (Milpitas, Calif.). "A lot of companies who are not TI, not ADI, Lucent or Motorola, are still interested in bringing DSP capabilities in house. We're here to help them," said Williams. Broadcom's license highlights the open nature of the agreement, he said, since Broadcom and LSI compete in many broadband markets.
Behind the buy
LSI's acquisition of ZSP in the spring of 1999 was in fact intended to support broadband applications, according to Giuseppe Staffaroni, vice president and general manager of the company's broadband communications division. "Growth in this area required a facility that we couldn't see in the market that's why we acquired ZSP," Staffaroni said. LSI Logic's licensing of the ZSP400 also puts it in competition with other DSP core providers, like DSP Group Inc. (Santa Clara, Calif.), Massanna (Campbell, Calif.) and 3DSP (Irvine, Calif.).
"We talked to a lot of people. We found OEMs liked the ZSP," said Williams.
Broadcom, which has considerable DSP experience of its own, hesitated to confirm what part types it intended to build with the ZSP core. (The ZSP processor has been promoted as an efficient device in speech-processing applications in many DSP conference papers.)
Ross Mitchell, vice president of Broadcom's packet telephony division, acknowledged that the ZSP core has a favorable programming model. Unlike many new-generation DSPs that utilize parallel hardware resources and a very long-instruction-word (VLIW) architecture to increase the amount of work done at each clock cycle, the ZSP is a pipelined superscalar architecture with a very fast clock. Though ZSP performance is contingent on programming skills, the architecture includes a five-stage pipeline with separate paths for data and instructions and all register locations are visible to a programmer.
VLIW DSPs like Texas Instruments' C6X family and Motorola's and Lucent Technologies' joint StarCore rely heavily on C compilers, which will never be 100 percent efficient. Thus, Mips for Mips, the ZSP400 core will be very com petitive in terms of code density, memory requirements and power consumption, said Williams. "Its performance falls in the sweet spot of the market somewhere between the top end of the TI C54X and the low-end C6X," he said.
The standard-product version of the 200-MHz ZSP core, the LSI401Z, outperformed the 120-MHz TI C549 and the 120-MHz Lucent DSP16210 in fast Fourier transform (FFT) benchmarks performed by Berkeley Design Technology Inc. (Berkeley, Calif.). Program memory usage for the three processors on a 256-point FFT test was very similar about 100 bytes. The 250-MHz TI C6202 outperformed all of its competitors on the FFT benchmarks but used 800 bytes of program memory.
LSI Logic said it is working on further iterations of the ZSP architecture that it will aim at low-cost consumer applications, and another that will support high-performance applications with faster clock rates. The ZSP400, meanwhile, is available as an RTL kit.