Cadence adds system-level design tool to EDA flow
Cadence adds system-level design tool to EDA flow
By Michael Santarini, EE Times
January 10, 2000 (11:17 a.m. EST)
SAN JOSE, Calif. Cadence Design Systems this week will become one of the first major EDA companies to grapple with the problem of system-level design when it releases the Cierto Virtual Component Co-design (VCC) product. Aimed at describing and refining a mixed hardware/software design at a very high level of abstraction, Cierto could fill a significant gap among design tools and put some zing in an emerging EDA tool category.
That segment electronic system-level (ESL) design is now largely served by the N2C system from CoWare (Santa Clara, Calif.). At a lower level, the QuickUse tool from Mentor Graphics Corp. (Wilsonville, Ore.) "provides the database portion of the core-based ES tool flow," said Gary Smith, chief EDA industry analyst at research house Dataquest Inc.
The Cadence entry which represents the long-awaited first fruits of the company's Felix collaborative research initiative covers fa r more ground. As a result, Smith said, "ESL just got a whole lot more interesting." Unlike today's hardware/software co-verification tools, Cierto VCC is used before, and during, hardware/software partitioning to map an abstract function into an architecture. It allows designers to integrate virtual components representing both hardware and software, and to explore complex hardware/software trade-offs, analyze product performance and evaluate product architectures early in the development cycle.
"Ten or 15 years ago, the EDA industry went from gate level to register-transfer-level abstraction and gained great productivity increases in the process," said Stan Krolikoski, group director of marketing for system-level products at Cadence. "Now, with this release, we are raising design to the next level of abstraction.
"Cierto VCC is the culmination of the Felix initiative," said Krolikoski, referring to the collaborative project chartered to take hardware/software co-design to new levels. "It pulls in all the technology we have been keeping under wraps for years and all the feedback our 15 VCC beta customers have given us over the last year and half. In that time we have made over 1,500 bug fixes, so this really is a polished and proven product."
"This is the year that system-level design is really making an enormous breakthrough," said Pete Hardee, director of product marketing at CoWare. "We were expecting this release and we welcome [Cierto]. It brings greater recognition to an EDA segment that we at CoWare have been serving for two years."
Hardee said the CoWare tool can halve the time it takes to move a design from sketch on a cafeteria napkin to working chip. N2C has built a loyal following at companies such as Alcatel, Fujitsu, Matsushita, Mitsubishi, Motorola, Nokia, Sony and STMicroelectronics, he said.
For its part, the Cierto VCC tool leads designers through the system exploration process via several phases of refinement, Krolikowski said, and precedes hardware/software co-verifica tion in the overall tool flow.
"What is the optimal mapping between the function I want to produce and the architecture I'm going to use to implement that function?" he asked. "That is what this tool is going to answer."
Krolikoski said beta customers that have evaluated the tool fall into mainly two categories: traditional system houses and semiconductor companies doing leading-edge system-on-chip designs. For example, he said, Hitachi Ltd. is looking at Cierto VCC as a delivery vehicle for its intellectual property. The company uses it to allow customers considering the various SH processors to evaluate the cores' performance in their systems. After they make the decision, Hitachi will add its drivers to the Cierto VCC for easy development, he said.
Krolikoski said systems companies like Ericsson are drawn to Cierto VCC because they want to develop a single platform for a product line. "The VCC will allow them to explore and add features at a top level to each generation product within that product line," said Krolikoski. "If the original designer leaves, the company still has the information for their design right there-organized and documented in a systematic way. This tool definitely gives you a bang for your buck."
Smith of Dataquest said Cierto VCC has given Cadence the lead, at least temporarily, in the ESL tools market.
"When they first announced Felix, it appeared the spec they were working toward was ridiculous. There were so many holes left in the flow," said Smith. "It wasn't until last year's Date [Design Automation and Test Conference Europe, held in Munich] that it became clear they were developing a flow that would close a huge hole in the software area."
Smith said until now, hardware/software co-design tools have focused on hardware, giving only lip service to software problems.
"We used to think that since you write the description in C code, you could just hand that code d own to the software guy and life would be easy," he said. "We thought [hardware developers] had the hard job, but as it ends up, the software guys write application C just like we would stare at C code and write VHDL there is no automatic connection. There is a hole in the software flow at basically the same level as [hardware's] RT level. What Cadence is trying to do with Felix is fill that hole."
Smith said Cierto gives Cadence a leg up over archrival Synopsys Inc., which took the EDA revenue crown from Cadence last year. "In my mind Synopsys dropped the ball on this," he said. "They were really late to jump on board."
However, said Smith, the fact that Synopsys CEO Aart de Geus has joined the board of directors of the Gigascale Research Center suggests the company aims to make up for lost time. Smith said the Gigascale Research Center "is doing the most important research in design today. It looks like Synopsys is starting to pay attention again."
N2C has different target Smith said th at while the Co-Ware tool, N2C, will compete with Cierto in some respects, it largely plays to a different market.
"Cadence is trying to address the entire design problem with full hardware and software co-design, while CoWare is really restricting the hardware problem so they can concentrate on the software problem," said Smith. "It is really apples and oranges."
The CoWare tool, he said, "fits better into the embedded-silicon market, where you are working with fixed architectures. Felix is really attempting to look at a much broader and tremendous problem, something people have been working on for the last 20 years. Cadence still has a ways to go but this a real good start."
CoWare's Hardee conceded that N2C does not address software estimation. But he said it does include higher-level functions such as mapping function to architecture. Future releases will capture behavior with graphics, he said. "[N2C] splits behavior and commutation and allows users to create a performance model of the com munication within the system," Hardee said. "You can explore bottlenecks and storage without needing the full functional spec. We also have the tools and methodologies to capture a system-on-chip platform."
As for the Mentor entry, Smith said, "A systems architect uses somewhere around four to six ideas at a time. Think of a database that can pull up 100 or more variations on an architecture, and identify the cores needed to design that product. That's what Mentor's QuickUse is trying to get to."
Smith expects new ESL tools to hit the market soon, filling the gaps in system-level design methodology. Companies with best-of-breed tools will grab market leadership, he said. He called Cierto "a great start at true hardware/software co-design, but it's still new. There are still many EDA tool opportunities [for other suppliers]."
Cierto VCC starts at $110,000 and runs on Unix and Windows NT platforms.
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