MILPITAS, Calif. -- September 23, 2008
-- Sonics Inc., a premier supplier of system-on-chip (SoC) SMART Interconnect™ solutions, today announced a webinar on how a multichannel DRAM subsystem can provide a scalable and memory efficient solution for the next generation of video SoCs. This webinar will provide information that will be valuable to architects and SoC design engineers.
The webinar is scheduled for Oct. 2 at 10 a.m. PST. There is no cost to participate.
The webinar will address:
- Digital video architecture requirements
- DRAM efficiency issues when moving to DDR3
- Multichannel DRAM architectures
- A solution to minimize the impact on software, when implementing a complex physical memory architecture
Sophisticated image and scaling algorithms for high-definition-video along with state-of-the-art compression standards such as H.264 are constantly pushing the limits of the memory subsystems with higher performance requirements. This webinar will provide valuable information on addressing these issues with multichannel DRAM subsystems. To register please visit: http://seminar2.techonline.com/registration/distrib.cgi?s=1312&d=723
Sonics Inc. is a premier supplier of SMART Interconnect solutions, delivering high SoC design predictability and increased design efficiency. Its solutions address the growing complexity found in consumer products with voice, data and video features. Major semiconductor and systems companies including Broadcom, Samsung, Texas Instruments and Toshiba leverage Sonics’ technology in leading products in the wireless, digital multimedia and communications markets. For more information, see www.sonicsinc.com