Aldec selected by Thales to deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System

HENDERSON, Nevada - September 25, 2008 - Aldec, Inc. announced today that Thales has decided to deploy the DO-254/ED-80 CTS(Compliance Tool Set) from Aldec. The DO-254/ED-80 CTS is an In-Hardware FPGA validation system developed to meet Level A-D requirements defined by the DO-254/ED-80 Design Assurance Guidance for Airborne Electronic Certification Manual. The deployment of the system has enabled Thales to validate for the certification authorities that the hardware implementation of an advanced avionics system’s RTL design is working correctly at the required speed in the targeted FPGA.

"Our project involved an Altera Cyclone® II FPGA with multiple clocks and speeds in excess of 128MHz. We wanted a complete verification path with requirements traceability and simulation results maintenance to validate that our system would work on the final hardware we deliver to our customer" said Eric Cardone, Program Manager at Thales Land & Joint Systems Division, "Aldec’s DO-254/ED-80 CTS gave us an effective way to meet the Level B Verification process requirements imposed by the DO-254 certification authorities."

"Specifying a complete test strategy to verify each of the system requirements is a very important part of the DO-254/ED-80 certification process" said Dr. Stanley Hyduke, President of Aldec. "The Thales engineering team used our DO-254/ED-80 CTS solution to verify that each requirement of the safety critical system was met on the end-target hardware, as it is required by Chapter 6.2 Verification Process of the DO-254/ED-80 specification. The solution was able to identify problems in the design and provide DO-254/ED-80 certification authorities the verification data required for Level B compliance."

"As worldwide enforcement of the DO-254 standard grows, Thales has taken a leadership role in the avionics industry by adopting the standard within its airborne electronic hardware systems," said Amr El-Ashmawi, senior business unit manager, military and aerospace, at Altera. "Aldec’s DO-254/ED-80 CTS In-Hardware FPGA validation system, along with Altera’s design flow and Cyclone II FPGAs, allow Thales to have an end to end solution that addresses DO-254 certification requirements. Altera and its DO-254 Global Partner Network, including Aldec, recognize the importance of providing companies like Thales a comprehensive DO-254 environment which will save them a significant amount of engineering time and development costs."

Thales Usage Model

Aldec’s DO-254/ED-80 CTS enabled Thales engineers to uncover and resolve design problems that were not visible using an event driven HDL software simulator. Aldec’s DO-254/ED-80 CTS utilized the actual end-target FPGA device and enabled the reuse of the same test vectors as for RTL simulation in order to validate that the designs operation in the final target hardware met the actual system speed requirements without the need for additional analysis as is the case with other verification solutions or prototyping. Utilizing the same test vectors for each stage of the design verification, Aldec’s DO-254/ED-80 CTS delivered time savings for requirements traceability and results analysis. The results from each of the tests were stored and documented to be used in the certification process as required by the DO-254/ED-80 Certification Manual. Furthermore, Aldec provided a full set of the tool tests for the qualification process according to DO-254/ED-80 specification.

DO-254/ED-80 Compliance Tool Set

The DO-254/ED-80 CTS solution from Aldec provides support for Levels A through D of the "Design Assurance Guidance for Airborne Electronic Hardware" (DO-254/ED-80) Chapter 6.2 "Verification Process" and Chapter 11.4 "Tool Assessment and Qualification Process". The DO-254/ED-80 CTS consists of a mixed language HDL Simulation tool suite and In-Hardware Simulation system that supports the customer’s specific FPGA, PLD, or ASIC target device providing functional verification and/or at-speed testing.

The verification flow requires the design first be checked in the HDL simulator to validate design’s functionality against requirements and then in the end-target FPGA hardware. A golden set of waveform vectors validated in the HDL simulation are automatically compared with the set of waveform vectors generated after in-hardware simulation in the end-target FPGA device. In-hardware testing provides assurance that the design works in the target device just as it did during HDL simulation, with full traceability of the hardware outputs back to the design requirements.

Independent Tool Assessment

In addition, In-Hardware testing provides independent assessment of outputs from logic synthesis, FPGA vendor place-and-route, and HDL simulation and code coverage tools, fulfilling the DO-254/ED-80 requirements for Level A and B certification requirements.

About Aldec

Aldec offers a patented technology suite including: design entry, HDL simulators, co-simulation, design rule checking, hardware-assisted verification, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions. www.aldec.com