Sarnoff Europe Releases Silicon-proven ESD Solutions for Advanced Applications in 40nm CMOS
Targeted and suitable for the specific design challenges of advanced consumer applications in 40nm, the silicon-proven ESD solutions feature extremely low power consumption (50pA leakage), enable high signal speeds (100fF linear ESD load) and provide high ESD performance for external pins (8kV HDMI).
“Together with the base foundry rules, our specialized complimentary ESD solutions enable product reliability and manufacturing yield for the leading edge applications in the world’s most advanced foundry process,” said Koen Verhaege, Executive Director of Sarnoff Europe. “This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design. This is especially so for the advanced applications such as wireless ultra-wide band, multi-media, mobile, network, game and FPGA applications.”
The Sarnoff proprietary 40nm CMOS ESD solutions are fully qualified for 2,000V Human Body Model (HBM), 200V Machine Model (MM), and solid (500V) Charged Device Model (CDM) robustness even for the most demanding applications. The solutions are available today. A GDSII library of clamps can be delivered off-the-shelf, or tailored to customer specifications. A complete TakeCharge Design Kit will be available for IO developers and IP integrators for SOC-NOC designs by October 31, 2008.
Sarnoff Europe strives to have silicon-proven ESD solutions available very early in the life cycle of each new leading process. As such, IC innovators can avoid the ESD hurdles and focus entirely on their individual design challenges and novel applications. More than 450 volume production ICs to date testify to the quality and versatility of the advanced ESD solutions provided by Sarnoff Europe.
About Sarnoff Europe
Sarnoff Europe headquartered in Gistel, Belgium, is a subsidiary company of Sarnoff Corporation – founded in 1942 as the RCA Laboratories. Sarnoff Europe assumes worldwide responsibility for the development and commercialization of Sarnoff’s TakeCharge® on-chip ESD protection IP.
|
Related News
- T2M is excited to announce the successful licensing of our partner's Silicon-Proven 1G Ethernet PHY IP Cores on a Tier-1 Foundry in Korea, using the advanced 14LPP process, in collaboration with a leading Tier-1 Korean customer
- Unlock seamless video transmission between graphics adapters and LCD displays with readily licensable, silicon-proven LVDS IP cores tailored for the advanced 22FDX process node
- Sofics Releases Analog IO's and ESD protection clamps for Advanced Applications using TSMC 7nm FinFET process
- Cadence Introduces New Family of Silicon-Proven High Performance Data Converter IP for Advanced 28nm Node
- HiSilicon Licenses eSilicon's 40nm Silicon-Proven TCAMs for High-Performance Network Chips
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Intel and Arm Team Up to Power Startups
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
- SmartSoC Solutions Joins TSMC Design Center Alliance to Boost Semiconductor Innovation in India
E-mail This Article | Printer-Friendly Page |