Palladium III Enables ARM to Speed Development and Integration of Its Processors by Addressing Verification Complexity Associated With Hardware and Software
SAN JOSE, CA -- Oct 07, 2008 -- Cadence Design Systems, Inc. , the leader in global electronic design innovation, announced today at the ARM Developers' Conference the availability of an ARM hardware/software co-verification environment that accelerates the system validation process and provides mutual customers with a faster path to first silicon working with early software. ARM designers have adopted the Cadence(R) Incisive(R) Palladium(R) III acceleration/emulation system for its advanced processor development, using it for both in-circuit emulation and transaction-based acceleration.
"The new environment, focusing on multimedia, graphics and network storage applications, enables our mutual customers to expand and accelerate their system validation ramp-up in these market segments in addition to the popular ARM processor-based handset market," said Peter Middleton, vice president of engineering, Processor Division at ARM.
The new environment is based on a reference design utilizing the Palladium III system, the ARM(R) RealView(R) Debugger, ARM processor IP and Cadence SpeedBridge(R) adapters. This environment demonstrates audio/video playback and capture of AVI and MP3 files, Web browsing, Linux boot and software debugging, and helps customers to ramp-up their ARM processor-based design system validation environment rapidly.
"Our Mobile-WiMAX/Cellular chip worked within hours after receiving our silicon back," said Yehuda Adelman, vice president of VLSI at Comsys. "Cadence's full-system validation solution enabled us to achieve our time-to-market goals. The Palladium series' fast bring-up and turnaround times, its hardware/software full-vision multicore capability, combined with the ARM RealView Debugger, helped us to reduce our development cycle. The new environment might further accelerate the hardware/software co-verification bring-up efforts."
ARM processors have traditionally been validated by ARM using the Cadence Palladium acceleration/emulation series.
Added Middleton: "Cadence's Palladium III system and its integrated verification solution provide the capacity, throughput, turnaround, and the bring-up time needed within real-world scenarios to verify our most advanced processor IP."
"After a successful deployment with our leading-edge graphic applications, we have proliferated the Cadence Palladium technology into our standard system validation process for our ARM processor-based portable navigation devices (PNDs) and mobile internet devices (MIDs)," said Narendra Konda, director of Engineering at nVidia. "This newly announced combined solution delivered by Cadence with ARM processor IP will help customers to quickly create a complete validation environment for the most complex designs in the market."
The Palladium series of accelerators/emulators provides the highest throughput for validation of complex hardware, software and full systems in the wireless, graphics, networking and consumer markets. The Palladium series supports ARM logic tiles (including the ARM7, the ARM9, the ARM10, the ARM11 and the Cortex processor families). By incorporating peripherals, embedded processors, multiple ASICs, embedded software, and real-world data, the system delivers MHz speed and is capable of handling designs of up to 256 million gates. The system delivers superior debug, system-wide management, and advanced verification automation features such as assertion- and transaction-based acceleration and can bring-up a new design to emulation in less than a week.
"The testimonials from ARM, nVidia and Comsys are evidence of the value proposition the Palladium series provides for both processor-based IP designers as well as ARM-based wireless system integrators," said Ran Avinun, marketing group director for system design and verification at Cadence. "Emulation continues to be the best method for validation of full SoC designs with embedded processors months before silicon tapeout -- reducing risk in committing to final silicon. The new integrated solution has been designed by Cadence in collaboration with ARM, with a focus on project teams that are building ARM processor-based SoCs for the multimedia, storage and networking markets."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.