Motorola Offers Public First Comprehensive Set of Semiconductor Reuse Standards as Part of System-On-Chip Technology
IP/VC Block Deliverables and Verilog HDL Coding standards added to list of Semiconductor Reuse Standards
AUSTIN, Texas - December 15, 1999 - Fulfilling a commitment made earlier this year, Motorola's Semiconductor Products Sector (SPS), a leader in embedded solutions, today announced the release of two additional standards in their Semiconductor Reuse Standards (SRS) series, creating the first comprehensive set of industry reuse standards for System-On-a-Chip (SoC) intellectual property (IP) modules.
By adding the IP/VC Block deliverables (Intellectual Property/Virtual Component) and the Verilog HDL (Hardware Descriptive Language) Coding standards, Motorola has become the first company to release a comprehensive set of reuse standards for flexible reuse of IP among and between individual chip designs. Motorola is making them available to companies, universities, IP providers and others, enabling them to utilize the same set of high-quality standards for their reusable design blocks that Motorola uses. Motorola is among the first to release an IP/VC Block deliverables standard, and the first major semiconductor manufacturer to release a Verilog HDL Coding standard.
"Motorola's SRS is one of the most impressive sets of VC/SoC Standards we've ever seen in terms of overall vision, completeness, consistency, content and clarity," said Larry Rosenberg, Chair of the Virtual Socket Interface Alliance (VSIA) Technical Committee, and Larry Cooke, founding Chair and on-going visionary for VSIA's On-Chip-Bus (OCB) Development Working Group (DWG), both acting as independent consultants in a visit to Motorola's SPS Austin site.
"Although VSIA does not have Register Transfer Level (RTL) coding standards/guidelines, so direct comparisons are not possible, Motorola's RTL standards have the appropriate goals of not only being synthesizable, but also reusable and easy to understand," continued Rosenberg. "These are based both on Reuse Methodology Manual (RMM) generic rules and Motorola real design usage experience. Significantly, they are designed to be checked automatically, and automatic checking tools are in development. Motorola appears willing to consider working toward a set of industry-wide generic rules by studying VC quality-rating scorecards, such as OpenMORE. We hope Motorola will drive industry-wide, consistent, generic coding standards for RTL. These could lead to future revisions of VC quality rating 'scorecards.' We believe such 'scorecards' need to be developed by the industry in a truly open development/enhancement environment driven by the real users of these 'scorecards.'"
These standards will support the soft IP development process. In conjunction with the IP Interface (IPI) standard released earlier this week, the Verilog HDL Coding and IP/VC Block deliverables standards will enable IP developers to create SRS compliant soft IP which can interface to Motorola's core architectures. All of the standards have been developed in close collaboration across the Motorola design community and EDA vendors. The standards process and structure are based on the industry best practices such as the Virtual Socket Interface Alliance (VSIA) and the Institute of Electrical and Electronic Engineers (IEEE).
The Institute for System Level Integration (ISLI), based at the Alba Centre in Scotland, will be incorporating aspects of the Motorola SRS into its MSc course in System Level Integration. Professor Steve Beaumont, director of the Institute, stated, "We welcome the decision by Motorola to release its standards externally. Access to material that documents current best-practice within the industry is essential to ensuring the relevance of postgraduate courses. We expect to use the Motorola standards in courses such as our "IP Block Authoring" module. This will extend further the successful collaboration between ISLI and Motorola." Currently, Motorola sponsors two full-time MSc students and one EngD student at ISLI.
The Verilog HDL Coding standard describes coding requirements such as coding styles, partitioning, naming conventions, allowed and disallowed constructs and testability aspects. This standard is based on the IEEE 1364.1 synthesizable Verilog subset, the Reuse Methodology Manual (RMM) of Synopsys/Mentor, as well as Motorola's direct design experience.
The IP/VC Block deliverables standard details the required IP deliverables for soft or hard IP and their respective data formats which need to be developed and delivered by the IP creator to the IP integrator. This sets the expectations for the transfer of IP. Furthermore, the standard defines a rich set of metadata (descriptions about the data) and a directory structure and naming conventions to be used to package the deliverables for transfer.
The SRS can be downloaded from the Motorola's SPS Web site at: www.motorola.com/semiconductors/srs
About Motorola As the world's #1 producer of embedded processors, Motorola's Semiconductor Products Sector offers multiple DigitalDNA' solutions which enable its customers to create new business opportunities in the consumer, networking and computing, transportation, and wireless communications markets. Motorola's worldwide semiconductor sales were $7.3 billion (USD) in l998. http://www.motorola.com/semiconductors
Motorola is a global leader in providing integrated communications solutions and embedded electronic solutions. Sales in 1998 were $29.4 (USD) billion. http://www.motorola.com/
# # #
Motorola and DigitalDNA are registered trademarks of Motorola Inc.
Editorial Contacts: Jeff Gorin Motorola (602) 952-3854
Melissa Weiss MS&L Global Technology (805) 230-8210 email@example.com
Reader Contact: Beth Gabrick Motorola (512) 342-6432