TSMC Adopts Mentor Graphics Calibre Physical Verification Tool Into Its SoC Design Flow
WILSONVILLE, Ore., Dec. 14 -- Mentor Graphics Corporation (Nasdaq: MENT) and Taiwan Semiconductor Manufacturing Corporation (TSMC) today jointly announced that TSMC has selected the Mentor Graphics Calibre® product line as the physical verification tool within its netlist sign-off flow for deep submicron designs.
TSMC adopted the Calibre product line because it delivers immediate availability of world-class Turn-Around Time (TAT) for large 0.25/0.18-micron System-on-Chip (SoC) designs fabricated across a variety of process technologies, including advanced logic processes, mixed-signal processes and various embedded memory processes. Customers of TSMC and Mentor Graphics can now complete multiple physical verification runs per day on SoC designs incorporating hundreds of millions of transistors. This translates into much faster completion of design and tape-out.
Customers can download high quality 0.18-micron, 0.22-micron, 0.25-micron and 0.35-micron Calibre rule files from the TSMC-Online customer information Web site at: http://online.tsmc.com.tw. Files are updated within seven days of a TSMC process rules specification revision, ensuring customers' ability to keep up with the rapid pace of process technology evolution.
``TSMC needs a physical verification solution up to the challenge of rapidly verifying multi-million transistor designs to give our customers the fastest possible turn-around time. Mentor's Calibre product line is that solution,'' said Mike Pawlik, vice president of Corporate Marketing for TSMC. ``Mentor Graphics, a key member of our EDA Alliance and part of our Virtual Fab strategy, has an impressive track record of continuous and significant enhancements to the Calibre tool's performance and capacity.''
``After a rigorous and demanding evaluation, we chose the Calibre product line as our internal sign-off tool for design services,'' said Fred Wang, Y.P. Chyn, director of TSMC's Design Service Division. ``This is significant not only because our customers can confidently hand-off their design to TSMC at netlist level, but TSMC has also paved the way for foundry customers to access our leading technologies. Mentor's Calibre product line gives unsurpassed design style independence, performance and capacity are certainly key enablers of that thrust.''
``We are proud to provide TSMC's customers with this new level of advanced tape-out support,'' said Wally Rhines, president and chief executive officer of Mentor Graphics Corporation. ``Mentor Graphics and TSMC have jointly developed, tested and delivered rule files for TSMC's advanced deep submicron technology for two years now, through Mentor's Design for Manufacturability (DFM) Silicon Partners program. TSMC's adoption of Calibre further strengthens this partnership.''
Mentor Graphics' partnership with TSMC extends beyond physical verification to deep submicron parasitic extraction. TSMC has adopted and supports Mentor Graphics xCalibre parasitic extraction and interconnect modeling tool for all processes with minimum features sizes of 0.18-micron and below.
New Industry Standard in Physical Verification and Manufacturability
In November 1999, Dataquest released a report confirming Mentor's Calibre tool suite as the market leader in physical verification. This report, entitled ``The IC CAD Market Continues to Change,'' announced Calibre's 40% market share for 1998. This is the third straight year of verification market share growth for Mentor Graphics, as the semiconductor industry accelerates its adoption of Calibre as the standard for physical verification.
Founded in 1987, TSMC is the first and largest semiconductor foundry company in the world. The company is based in Taiwan's ``Silicon Valley,'' the Hsin-Chu Science-Based Industrial Park, and is dedicated to providing manufacturing services for advanced integrated circuits to fabless design houses and integrated device manufacturers (IDM). The company operates two 6-inch wafer fabs and three 8-inch wafer fabs offering a comprehensive set of IC fabrication processes, including processes to manufacture CMOS logic, mixed mode, volatile and non-volatile memory and BiCMOS chips. In mid-1996, TSMC began construction on the first-ever, pure-play foundry in the US, WaferTech, in Camas, Washington -- a $1.2 billion joint venture. Fab 6 and 7 will be located in the new Tainan Science-Based Industrial Park in Taiwan.
About Mentor Graphics Corporation
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $500 million and employs approximately 2,600 people worldwide. Company headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: www.mentor.com/dsm.
NOTE: Mentor Graphics, Calibre is a registered trademark of Mentor Graphics Corporation. All other product or company names are the registered trademarks or trademarks of their respective owners.
CONTACT: Janet Martin of the Benjamin Group/BSMG, 415-352-2628, or firstname.lastname@example.org, for Mentor Graphics; or Tyler Magee, Marketing Communications of Mentor Graphics, 503-685-0309, or email@example.com.