CAMPBELL, Calif., October 16, 2008
-- Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, announces the availability of their Gigabit Ethernet MAC (GEMAC) SystemVerilog Open Verification Component (OVC)
supporting multi-language verification environments. The GEMAC OVC is the latest addition to the portfolio of Silicon Interfaces Verification IPs which combines proven methodology, robust multi-language interfaces, and powerful verification technology into a highly reusable verification component.
The GEMAC OVC VIP is fully documented, off-the-shelf component for the verification of the Gigabit Ethernet MAC. Full Programmability and versatility of the OVC enables connection to any standard IEEE 802.3 based GEMAC device and supports application of Stimulus to the generic microcontroller Interface as well as PHY Interface. The GEMAC OVC provides a concise, declarative mechanism to code the specification of sequences of events and activities of Gigabit Ethernet MAC Protocol. This methodology provides the best framework to achieve coverage driven verification.GEMAC OVC
is developed using the OVM Class Library that includes ovm_sequence, ovm_driver etc. base classes and capabilities to create modular, reusable components. This methodology combines automatic test generation, self-checking test benches and coverage metrics to significantly reduce the time spent verifying a design under test.
Silicon Interfaces’ GEMAC core implements the Ethernet Media Access Control (MAC) protocol according to IEEE 802.3 specification. The MAC has a standard Gigabit Media Independent Interface (GMII) to connect to any PHY interface. The core can be used in various integrated applications. A single channel MAC with PCI controller would provide an ideal solution for inexpensive NIC cards.Product Highlights:
- Fully OVM-compliant and completely configurable with SystemVerilog environment, as per user requirements and the OVM User Guide for OVC’s.
- Abstract, Modular IEEE 1800 SystemVerilog test benches.
- Coverage driven verification method with ATPG and coverage metrics.
- OVM based transactions using monitors, checkers and scoreboards.
- OVM based Coverage model implemented for all transaction types.
- Extensive Checking of the Physical (PHY) interface for the MAC
- Accurately verifies IEEE 802.3 standard Gigabit Ethernet MAC specifications.
- Application of Stimulus to the Generic Microcontroller Interface as well as PHY Interface.
The Gigabit Ethernet MAC SystemVerilog OVM-compliant OVC VIP is available now.About Silicon Interfaces
Silicon Interfaces offers Designs Services by Onsite Contract Consulting, Offshore Projects, Virtual Development Services (VDC) as well as many silicon optimized IPs across multiple domain such as Networking, Data Communications, Interconnect, Embedded and Storage, primarily in the areas of System Verilog/Verilog/VHDL/SystemC for Design, Modeling and Verification of complex SoC, ASIC and FPGAs. We offer extensive Verification Programs based on SystemVerilog, E Language, Vera, Verilog and VHDL, wherein we have developed e Verification Components, OVAs, Verification IP and Verification Test Benches.
Since July 2001, Silicon Interfaces promoted an IP Development Program - Silicon Cores: Core to the Intelligent SystemsTM. We have IPs such as Bluetooth Baseband, 802.11 a/b/g MAC & Baseband, Gigabit Ethernet MAC, Sonet STS 1/3 Framer, 1394, USB2 Function Controller, USB On-the-Go, Infiniband, Rapid IO, 8530, 8051, 7990 and UART. The company offers Verification IP solutions using industry standard methodologies.