Endeavor Intertech Corporation to Provide Accurate High Performance Models of Complex Cores for Synopsys Eaglei Hardware-Software Co-Verification Environment
HILLSBORO, Ore.----Dec. 10, 1999--Endeavor Intertech Corporation announced today that it will work with Synopsys to develop co-verification models on a wide range of processor core architectures.
Under terms of the agreement, Endeavor Intertech will develop and integrate instruction set simulator models, bus functional models, and test suites into the Synopsys Eaglei® product line. Synopsys will distribute the models as part of its hardware/software co-verification offering. The first models developed under the agreement will be of the IBM PowerPC 405(TM) core.
Hardware/software co-verification with the Synopsys Eaglei environment allows designers to significantly reduce design time and improve product quality and by allowing software to be run on hardware long before physical prototypes are built. This essential capability is rapidly becoming a requirement for the successful verification of complex system-on-a-chip (SOC) designs.
The current industry standard models for co-verification generally offer poor representations of processor core functionality. The ability to accurately mimic the hardware cycle-by-cycle, pin-by-pin is either too complex or considered too time consuming for most modelers. However, ignoring these model details seriously constrains the usefulness of co-verification systems.
``Our goal is to continue to raise the industry bar for accuracy and performance in hardware/software co-verification,'' said Dr. Geoffrey Bunza, vice president of Synopsys' Large Systems Technology Group. ``We believe that it is necessary -- and Endeavor Intertech has demonstrated that it is possible -- to produce software models that are cycle-accurate.''
Endeavor Intertech has designed a simulation framework that accelerates the process of modeling, even as it enforces the appropriate accuracy upon the model. The result is an instruction set simulator that, when integrated with Synopsys Eaglei, fulfills the promises of co-verification.
Endeavor Intertech's models, built upon its high-performance simulation framework, maintain 100% cycle or sub-cycle accuracy, while simulating at a rate of 150,000 to 250,000 instructions per second on a standard PC. Moreover, Endeavor Intertech has developed a method for users to enhance the functionality of the simulator by adding peripheral models that are dynamically instantiated in the simulation, thus providing a uniquely extensible simulation environment.
Although features are important, Endeavor Intertech is just as concerned with making sure the model is correct. ``We believe simulation model validation is a crucial concern for co-verification,'' said Dan Budge, vice president and CTO of Endeavor Intertech. ``We test our simulators against the original test vectors from the processor designers whenever possible, in addition to using their functional and timing tests. This insures that our simulators work exactly like the real thing, even to the level of pipeline bus cycles and multiple parallel busses.''
In addition to the co-verification model of the PowerPC 405 which will be distributed by Synopsys as part of its hardware/software co-verification offering, Endeavor Intertech will market a standalone version of its IPSim(TM) PPC405 model for software developers. Endeavor Intertech's models are available for Windows and Unix workstations. The Synopsys model supports most major hardware design and software development environments. The PowerPC 405 models will be available by the end of the year.
About Endeavor Intertech Corporation
Endeavor Intertech develops world-class high performance, cycle-accurate instruction set and intellectual property simulators that can be applied to hardware/software co-verification, co-design, or as standalone instruction set simulators for software developers. Endeavor Intertech develops these and other software tools for DSP, VLIW, RISC, and other embedded cores and processors for its EDA and processor design customers.
For more information on Endeavor Intertech's high performance, cycle-accurate simulators, please contact your Endeavor Intertech representative at email@example.com, or 503/628-6200. See Endeavor Intertech on the web at http://www.endeav.com.
About Synopsys' Eaglei Co-Verification Tools
The Synopsys Eaglei hardware/software co-verification tools are part of a powerful suite of high-level verification products and services which also includes VCS(TM), the industry's fastest Verilog simulator, Cyclone®/VSS(TM) for high-performance VHDL simulation, a comprehensive range of proven Logic Modeling® IP models for simulation, and the VERA(TM) testbench automation and analysis products to help designers meet the challenges of complex system verification.
For more information on Synopsys verification solution, contact your local Synopsys representative, visit the Synopsys website at: www.synopsys.com/verifyit email firstname.lastname@example.org, or phone 800/346-6335.
Note to Editors: IPSim is a trademark of Endeavor Intertech Corporation. Synopsys, Logic Modeling, Cyclone and Synopsys Eaglei are registered trademarks, and VCS, VSS, and VERA are trademarks of Synopsys, Inc. PowerPC and PowerPC 405 are trademarks of IBM. Other brands and products referenced herein are the trademarks or registered trademarks of their respective holders.
Contact: Endeavor Intertech Corporation
David N. Glass, 503/628-6200 x100