HyperCore Architecture Overcomes Historical Challenges to Widespread Adoption of Manycore Technology
Tokyo, November 6, 2008 - Plurality Ltd., a developer of advanced manycore processor solutions, today announced at the Multicore Expo Japan 2008 the beta release of an extensive set of development tools for its HyperCore™ Architecture Line (HAL) of manycore processors. The tools will facilitate the evaluation and widespread adoption of Plurality’s technology. Manycore architecture – from tens to thousands of cores per processor – is widely acknowledged as the natural evolution of multicore processing. HAL processors will offer the highest performance at the lowest price per watt per square millimeter of any chip-level shared memory machine currently on the market.
“With multicore already mainstream, the future of computing inevitably will require massive parallelism performed on manycore processors,” said Plurality CEO, Igor Pe’er. “Because HyperCore is a comprehensive hardware and software manycore solution, it meets the need for a viable, standard platform for low-cost, massively-parallel processing.”
Positioned as a general-purpose accelerator for applications with a high degree of inherent parallelism, HyperCore acts as an extension of the most popular processor architectures (x86, PowerPC, and ARM). The HyperCore architecture includes 16-256 cores and multi-ported L1 shared memory in which each core is equidistant from the memory. A key component of the architecture is a hardware-based, low-latency, high-throughput synchronizer/scheduler that manages the cores according to a task map and balances the load among the cores. The synchronizer/scheduler ensures scalable performance that enables nearly linear speedup, regardless of the number of cores in the processor. Among the many applications ideal for the HyperCore processor are image and video processing, video surveillance, gaming, network processing, security, and software-defined radio.
“Plurality’s HyperCore will give us tremendous value – at least 10 times the performance of our current computing solution,” says Dekel Tzidon, head of research and IP development at BVR Systems Ltd. (OTCBB: BVRSF.OB), where Plurality’s manycore emulator is under evaluation for parallel processing in military simulation systems. “With Plurality’s programming model we will be able to quickly recompile over one million lines of application code to run on a manycore processor without major changes. We also can significantly reduce the hardware, software and operating costs of our simulation systems with Plurality’s acceleration boards.”
The HAL toolset includes a cycle-accurate simulator that runs on an x86 platform (Linux and Windows OS); a GCC cross-compiler (v. 4.0.1); GNU Binutils v. 2.18; a cross-debugger that works within the Eclipse development environment; and an emulator supporting Linux and Windows native environments. The tools enable a gradual approach from exploring parallel decomposition with the emulator to precise evaluation of the performance of a 256-core system with the simulator. Plurality's serial-like task-oriented programming model enables developers to easily write code for computations that are offloaded from the main processor. It simplifies the recompilation of serial code to parallel code and enables intuitive parallel programming of new applications.
Plurality’s manycore development tools are currently being evaluated at the University of Otago in Dunedin, New Zealand. Stuart Barson, business manager in the university’s Research and Enterprise Office, says, “We are excited to work with Plurality's emulator and look forward to receiving the simulator, so that we can learn how to readjust our algorithms.”
Several labs in the Electrical Engineering department at the Technion – Israel Institute of Technology in Haifa, Israel also are checking the tools. According to Peleg Aviely, Plurality’s vice president of engineering, “The Technion is very interested in our implementation of shared L1 cache memory, whose traits are reminiscent of a Parallel Random Access Machine (PRAM), and in our hardware synchronizer/scheduler, which lets the programmer focus on concurrency instead of synchronization and communication issues.”
Plurality is developing acceleration boards that interface to a main CPU via a PCI Express connection and AMD’s (NYSE: AMD) HyperTransport™ link. Plurality is a partner in AMD’s Torrenza initiative, which enables hardware manufacturers other than AMD to connect a co-processor to an open CPU slot on the AMD Opteron 64 via its HyperTransport link. Daniel Daniel, country manager of AMD Israel, says “AMD is pleased that Plurality supports the Torrenza initiative. We believe Plurality offers an excellent solution for customers who need to accelerate applications requiring massively-parallel processing.”
Pricing and Product Availability
The beta version of Plurality’s development tools is available immediately at no charge and can be downloaded from http://www.plurality.com/download_form.html. Plurality will release an FPGAbased 32-core evaluation board during Q2, 2009. A 64-core chip (HAL-64) will be introduced during the second half of 2009, along with an acceleration board that includes the HAL-64 processor. For further information, please email the company at firstname.lastname@example.org or visit www.plurality.com.
Plurality develops advanced Intellectual Property, chips and acceleration boards for manycore processing. Plurality’s IP is based on a scalable, easily-programmable, manycore processor that is positioned as a general-purpose accelerator. The processor delivers the highest performance and lowest cost per watt per square millimeter of any currently available chip-level shared memory machine. The privately-funded company is headquartered in Netanya, Israel. HyperCore is a trademark of Plurality Ltd. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.