0-In verification monitor checks HyperTransport protocol
![]() |
0-In verification monitor checks HyperTransport protocol
By Michael Santarini, EE Times
November 27, 2001 (12:39 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011127S0029
SAN MATEO, Calif. Tool vendor 0-In Design Automation Inc. has released a version of its CheckerWare monitor for the HyperTransport I/O Link Protocol standard. 0-In said the HyperTransport monitor will help designers develop chips that use the protocol. Developed largely by Advanced Micro Devices Inc., HyperTransport technology provides a low-latency, low-pin-count, high-speed link between chips inside computers and communication devices, and is said to make interaction between devices up to 48 times faster than some existing bus technologies. The 0-In development team used AMD's simulation environment to ensure that its HyperTransport monitor complies with the latest version of the HyperTransport I/O Specification. The protocol monitor is essentially an executable specification for the HyperTransport standard, and therefore is likely more precise and accurate than t he written document itself, 0-In said. A customer has used the HyperTransport monitor successfully in a design, the company said. The monitor supports many modes and features of the HyperTransport Protocol, including End, Node and Bridge implementations, all CAD widths, error handling and low-level link initialization.
Related News
- Mentor Graphics Delivers Enhanced 0-In Clock Domain Crossing and Formal Verification Technology
- Renesas Technology Integrates Mentor Graphics 0-In Assertion Synthesis for Assertion Based Verification Flow
- 0-In Boosts Efficiency of Coverage-Driven Verification with Structural Coverage and Formal Analysis
- 0-In Introduces Breakthrough Automatic Verification of Metastability Effects
- 0-In's Archer Verification System Targets Verification Hot Spots
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |