WILSONVILLE, Ore.-- January 15, 2009
-- Mentor Graphics Corporation (Nasdaq:MENT - News) today announced that Fujitsu Limited and Fujitsu Laboratories Limited have selected Mentor Graphics’ Questa® advanced functional verification platform, to deploy their next generation functional verification environment based on the Open Verification Methodology (OVM). With Fujitsu’s preference for open standards, the OVM provides the ideal means to ensure the highest levels of productivity and reuse for the verification of Fujitsu’s state of the art chip designs.
Fujitsu and Fujitsu Laboratories adopted the IEEE Std. 1800-2005 SystemVerilog language and the OVM to verify a complex, multi-clock domain SoC that can form a key element of Fujitsu’s high-performance parallel computer system. Fujitsu’s and Fujitsu Laboratories’ verification environment features an advanced UML front-end to the OVM that facilitates specification driven verification of multiple SoCs. The design specification is analyzed to extract use cases systematically and exhaustively that form verification scenarios.
“Fujitsu’s strategy to deliver highly reliable computing and communications products requires advanced verification techniques and very high coverage,” said Aiichiro Inoue, president of the Next Generation Technical Computing Unit at Fujitsu Limited. “Working with Mentor and the OVM makes advanced verification with SystemVerilog nearly vendor-independent and, thus, a promising path to follow.”
SystemVerilog coding techniques offer greater efficiency and ease of use for testbench creation. Fujitsu and Fujitsu Laboratories’ verification team used the SystemVerilog hierarchical interface mechanism to create an explicit hierarchy of interfaces that was then used by the OVM to drive the transactor that drove stimulus to the device under test.
“Users have confidence in OVM because it works on a number of commercial verification platforms, and they realize the healthy, growing design and verification ecosystem supporting OVM provides them the confidence to adopt SystemVerilog,” said John Lenyo, general manager of Mentor’s verification business unit. “We are pleased with Fujitsu’s and Fujitsu Laboratories’ decision to select Questa and OVM to solve one of their most challenging verification problems.” About the Open Verification Methodology (OVM)
The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open, and includes a robust class library and source code that is available for download. Visit http://www.ovmworld.org
for more information. About Mentor Graphics
Mentor Graphics Corporation (NASDAQ:MENT - News) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $850 million and employs approximately 4,450 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com