Intended Design Behavior Is Captured and Preserved, Reducing Life Cycle Design Costs and Verification Time While Enabling Efficient Knowledge Transfer and Design ReuseMOUNTAIN VIEW, Calif. -- January 19, 2009
-- Jasper Design Automation, provider of the most advanced formal technology solutions, today announced ActiveDesign™ with Behavioral Indexing™, the first EDA solution for behavior-based RTL analysis and verification by designers. Powered by formal analysis and Jasper’s new Behavioral Indexing technology, ActiveDesign delivers dramatic breakthroughs in design comprehension, driving higher RTL design quality and greater designer productivity. Jasper’s Behavioral Indexing technology enables ActiveDesign to iteratively extract, index and store relevant design behaviors, along with the RTL, in a dynamic, executable database referred to as the Activated Design™. Activated Designs are optimized for complex yet flexible behavior-based analysis and automatic regressions, and work seamlessly with Jasper’s formal property verification system, JasperGold®. Behavioral Indexing enables companies to capture and preserve the intended behaviors of a design as it is being implemented. In addition, ActiveDesign reduces verification time, accelerates knowledge transfer, improves design maintenance, and enables efficient reuse.
Primarily aimed at logic designers, ActiveDesign is used to confirm and index intended functional behaviors as the RTL is composed, and to easily validate complex, sometimes unintended, interactions among behaviors. This use mode is sometimes referred to as a “Designer Self Test.” The powerful comprehension features in ActiveDesign help designers and verification engineers that ‘inherit’ a design to become intimately familiar with relevant design functionality, without any access to the original design author. Activated Designs empower any user over the life of the design, or its derivatives, to comprehend, safely modify, and retarget the RTL design for new uses.
“Engineers have been looking for new technologies to increase the quality of their work prior to handoff to the verification teams, but without the overhead of developing their own testbench,” said Kathryn Kranen, Jasper’s president and CEO. “ActiveDesign enables engineers to produce higher quality designs, and greatly reduces the overall engineering effort, by finding problems with design behavior much earlier in the design cycle. In addition, ActiveDesign dramatically improves the ability of engineers to reuse RTL through the increased comprehension in an Activated Design. The response from pre-production customers has been excellent, highlighting the real need for greater automation during RTL development.”
ActiveDesign is complementary with all existing design flows and accepts RTL designs in SystemVerilog, Verilog, or VHDL. Waveform representations of design behaviors are automatically produced without a testbench or simulator using formal technology. Users can also refine the waveforms directly to describe desired behavior. ActiveDesign then indexes relevant design behaviors in a database, enabling dynamic behavior-based analysis and correlation of functional behaviors to the evolving RTL. The user runs “implication analysis” which automatically produces reports to show the impact of design changes on the indexed behaviors, classifying the behaviors as “unaffected”, “potentially affected” (temporally changed), or “broken”. These reports enable the designer to easily preserve desired behaviors while iteratively developing the design, or modifying it for a new use.Pricing and Availability
ActiveDesign will be available worldwide in March of 2009. ActiveDesign list prices start at $140K. For complete product and pricing details, please call +1.650.966.0245.First Public Demonstrations of ActiveDesign at the EDS Fair in Japan, booth #508
Learn more about ActiveDesign during the Electronic Design and Solution Fair (EDS Fair) at the Pacifico Yokohama in Kanagawa, Japan. CyberTec, Jasper’s exclusive distributor in Japan, will be providing the first public demonstrations of ActiveDesign in booth #508 on January 22nd and January 23rd, 2009. CyberTec will also present a seminar at EDS Fair on the benefits of ActiveDesign, including designer self-test. The seminar, which will be held January 22nd from 11:30 to 12:15, and January 23rd from 13:30 to 14:15, is titled, “New product announcement from Jasper - Jasper pioneers the new market for formal technology.” EDS Fair visitors can also view demos of the latest release of the JasperGold® Verification System and JasperGold® Express.About Jasper Design Automation
Jasper is a privately-held EDA software company leveraging formal technologies to deliver high value solutions for the design and verification of electronic systems and semiconductors. The company delivers products utilizing advanced formal analysis and Behavioral Indexing™ technologies to the global electronics market. Jasper is headquartered in Mountain View, California, and has offices and distributors located in North America, South America, Europe, and Japan. Visit Jasper online at http://jasper-da.com