Independently Certified Results Validate Performance, Power, and Size of the Coreworks ® SideWorks™ Reconfigurable Architecture.Lisbon, Portugal -- January 21, 2009
– Coreworks S.A., a leading provider of reconfigurable multimedia and communications IP blocks, today announced certified BDTI DSP Kernel Benchmarks™ results for its Mid-Grain Array Reconfigurable Architecture based upon the SideWorks technology. These results have been obtained for a DSP block, dubbed CWcomp4465, built with a SideWorks data engine tightly coupled with FireWorks™, a simple 32-bit RISC processor, also property of Coreworks. This is the first reconfigurable licensable core to be independently benchmarked using the BDTI DSP Kernel Benchmarks, allowing it to be compared with instruction-based processors and DSP cores. In summary, CWcomp4465 proved to consume up to 2 times lower power and 4 times smaller silicon area at competitive performance levels, when compared with other DSP cores running the same benchmark suite.
Coreworks will focus on licensing ready-made SideWorks applications, starting with a line of multi-channel audio encoders and decoders, and FFT cores. The SideWorks tools include an RTL automatic generator, a programming tool and a cycle accurate simulator. Moreover, Coreworks guarantees high code coverage RTL testbenches, FPGA prototyping and functional verification of its IP blocks. The architecture and tools ensure rapid design of subsystems whose correctness is guaranteed by automation of the design process. Coreworks offers high quality design services, accelerated by using its architecture and tools, and performed from its design center in the heart of Lisbon, Portugal.
The BDTI DSP Kernel Benchmarks™ is a suite of 12 DSP algorithm kernels that represent key building-block operations found in most signal processing applications.
Working at only about 200 MHz, the CWcomp4465 instance requires as little as 0.7 mm2 of silicon area and consumes as little as 49 mW of power in a TSMC CL013G process using the ARM® Artisan SAGE-X library.
When compared to the competition, this ultra small size and ultra low power core shows an impressive BDTIsimMark2000™ performance score of 2440. The BDTIsimMark2000™ is a composite DSP speed metric based on the execution time required to run the BDTI DSP Kernel Benchmarks™ suite. Since the CWcomp4465 works at a low frequency, the relatively high BDTIsimMark2000™ performance score is a result of the high level of parallelism of the SideWorks engine. See Table 1 below for detailed comparisons with other certified architectures.
"DSP performance, scalability, low power and low cost are key ingredients for the fast growing smart phone and mobile internet device markets, and Coreworks has demonstrated those capabilities", said Will Strauss, market analyst with Forward Concepts Co.
All scores based on worst-case clock speed for the TSMC130G process and ARM Artisan SAGE-X library.
|Company || ARM || CEVA || MIPS || Tensilica || Verisilicon ||Coreworks |
|Core || ARM9E ||X1620 || MIPS32 24KE || 545CK || ZSP500 ||CWcomp4465 (*) |
|Frequency [MHz] || 265 || 330 ||335 ||230 ||205 ||209 |
|Area [mm2] || 1.7 || 2.6 || 2.0 || 2.8 || 2.2 || 0.7 |
(Higher is better)
| 550 || 2660 || 1000 || 3820 || 1620 || 2440 |
|Memory Use Efficiency: |
(Higher is better)
| 72 || 67 ||73 || 69 || 68 ||48 |
|Power [mW] ||-- ||132 || 134 || -- || 62 || 49 |
* Coreworks scores include both a customized SideWorks DSP engine and the FireWorks 32-bit RISC processor. The SideWorks core used to implement the BDTI DSP Kernel Benchmarks includes four 16-bit multiplier units, six 32-bit ALUs, five shift units, six data multiplexing units, two data de-multiplexing units, two bit-reverse units, a bit unpack unit, and 6K bytes of memory. Different versions of the SideWorks core will yield different performance, power consumption, and die size figures than those reported here.Table 1. BDTI scores against competition (see www.bdti.com)
In an article in its InsideDSP.com newsletter, BDTI stated: “The CoreWorks' result is particularly impressive given the relatively low clock speed at which its cores are running coupled with very low area requirements and low power consumption.”. [Read the full BDTI article here
José T. de Sousa, Coreworks’ founder and CEO, said: "Coreworks partnered with BDTI as a means to have credible and independent information about the area and power efficiency of our high performance SideWorks™ technology. BDTI’s strict and fair evaluation and certification process, will help us consolidate our leadership role in serving customers requiring cost effective and low power solutions for multimedia and communications SoCs.”About the SideWorks™ technology
Sideworks™ is a patent pending architecture template ideal for multimedia, communications and DSP applications in general. The Sideworks™ template permits automatic generation of computational engines (SideWorks instances) by means of our internal SideGen™ software design tool. Other internal software tools include SideConf™, a programming tool for SideWorks instances, and SideSim™, a cycle accurate simulation tool.
SideWorks can be used for hardware acceleration of software bottlenecks in embedded processors, or as a stand-alone block implementing one or more functions which can be reconfigured at runtime. These functions are called SideWorks Kernels and Coreworks makes available a set of ready to use SideWorks Kernels for multimedia, communications and DSP applications in general.
When used as an accelerator, the companion embedded processor can be any commercial processor, interacting with SideWorks instances through the system bus in a straightforward way: configure the instance with the function to be performed, send the data to be processed and collect the processed data. Coreworks also provides FireWorks™, a proprietary configurable embedded processor which permits the inclusion of custom instructions and is tightly integrated with SideWorks instances.
Solutions implemented with the SideWorks™ technology are very competitive as they achieve low power consumption and small silicon area, significantly reducing the cost of the SoC. A more conventional instruction-based DSP or multi-processor solution may be 2 times less efficient in terms of power and 4 times less efficient in terms of area, as our certified DSP benchmark results demonstrate.About Coreworks® S.A
. Coreworks® S.A
) is a leading provider of Intellectual Property (IP) blocks for multi-standard multimedia and communications applications, targeting emerging applications such as satellite radio, DTV, IP-Phone, MP3 and other portable audio players, mobile devices, soft radio, communication gateways and more. Our IP products have been implemented in a wide variety of products, and in various process geometries, and are classified in three families: SideWorks (see above), AudioWorks and Core Access Networks. AudioWorks™ is a low-power and area optimized family of digital audio IPs, licensed by more than 30 companies worldwide. AudioWorks covers most of digital audio interfacing needs (SPDIF/AES-EBU, TDM, I2S), as well as audio Asynchronous Sample Rate Conversion. AudioWorks is the most complete and verified solution in the market, implemented using our state-of-the-art digital techniques for clock and data recovery. Core Access Networks® is Coreworks' patented technology for communicating with designs being prototyped in one or more FPGAs. Our FaceWorks™ IP block interfaces with an external Ethernet PHY, and permits observing and stimulating IP blocks in the FPGA, over the network, using a regular PC. A software API for the PC permits sending and receiving data to the FPGA as well as controlling this infrastructure.