Tality Standardizes on Verification Leader TransEDA For Design and IP Qualification
TransEDA's VN-Cover and VN-Check Central to Tality’s Qualification Process
London and Los Gatos, Calif. - November 26, 2001 - TransEDA - PLC (LSE: TRA), the leader in ready-to-use verification solutions, today announced that Tality Corporation, the world’s largest electronic product development outsourcing provider, has standardized on TransEDA’s VN-Check[tm] and VN-Cover[tm] as the HDL design rule checking and coverage analysis solutions in Tality’s intellectual property (IP) qualification flow.
Tality provides engineering services and IP to leading and emerging technology companies. With more than 800 engineers worldwide, Tality offers expertise in all aspects of electronic product design: complete systems, subsystems, and advanced integrated circuits. Tality’s growing portfolio of IP includes a wide range of communications IP blocks and integration platforms. The portfolio ranges from elements as complex as a complete Bluetooth platform to blocks as simple as a watchdog timer.
One of Tality’s key strategic initiatives is to increase design reuse and shorten the time to develop shrink-wrap IP solutions. Selecting TransEDA’s HDL rule checking and coverage analysis solutions for its IP qualification flow was a key component of this initiative.
According to Phil Rose, manager of the Tality IP team, “Our comprehensive IP platforms include Tality proprietary components and third-party IP from multiple suppliers. Therefore, ensuring that they all will work seamlessly together is highly complex. TransEDA’s verification solutions provide the objective feedback on the quality of our verification. They help us to reliably and repeatedly deliver high-quality designs and IP to our customers.”
VN-Cover is a comprehensive coverage analysis solution for both Verilog and VHDL designs, and is not dependent on any particular simulator. Of particular importance to Tality was VN-Cover’s condition coverage. “Some designers will write HDL as simple IF THEN ELSE clauses that break down into conditions covered by branch and statement coverage. Other designers write in more complicated ways, and condition-coverage accommodates a variety of coding styles and methods,” said Rose.
VN-Check is a configurable HDL checker for both Verilog and VHDL designs with over 1,000 pre-defined rules which can be organized into separate “databases” to facilitate sharing and re-use of coding standards on a project or company-wide basis. “We like VN-Check because the rules database is easy to customize and it isn’t dependent on a particular simulator. We base the rules on the `Best Practice’ database supplied and adjusted them to meet our own company style,” Rose added.
Commenting on the announcement, Tom Borgstrom, vice president of marketing at TransEDA said, “The use and re-use of IP is crucial for accelerating the increasingly complex task of system-on-a-chip integrated circuit design. An objective and repeatable means of qualifying design IP is essential for this. We are pleased that Tality has selected TransEDA’s solutions for this central role in their IP qualification process.”
Verification Navigator® Environment
VN-Check and VN-Cover are part of TransEDA’s Verification Navigator integrated design verification environment. It provides a common interface and use model for a suite of best-in-class verification solutions. Verification Navigator also includes VN-Control for application-specific test automation and VN-Optimize for test suite analysis. Verification Navigator integrates easily with leading simulators and existing verification environments and is available on the Solaris, HP-UX, AIX, Linux, and Windows platforms.
Tality Corporation, a subsidiary of Cadence Design Systems, Inc. (NYSE: CDN), is the world's largest electronic product development outsourcing provider. Leading and emerging technology companies around the globe leverage Tality's engineering services and intellectual property for the design of complex electronic systems and integrated circuits. Tality is headquartered in San Jose, California. For more information about Tality, please visit us at www.tality.com.
TransEDA PLC (symbol TRA on the London Stock Exchange) develops and markets ready-to-use verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company’s verification IP library includes models for advanced microprocessors and bus interfaces.
TransEDA’s design verification software performs application-specific test automation, configurable HDL checking, functional, finite state machine (FSM) and code coverage analysis, and test suite analysis. TransEDA’s tier-1 list of customers includes 18 of the world’s top 20 semiconductor vendors. For more information, visit www.transeda.com or contact TransEDA at 983 University Avenue, Building C, Los Gatos, California 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, email firstname.lastname@example.org.
Note: TransEDA and Verification Navigator are registered trademarks and VN-Check, VN-Cover, VN-Control, VN-Optimize, Simulation Edge and Foundation Models are trademarks of TransEDA. All other trademarks are properties of their respective holders.
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