IP News  

 

Synopsys and Mentor Graphics Release "OpenMORE" Reference Program for Evaluating IP Design Reuse and Verification
OpenMORE Builds Designer Confidence in Reuse Success of Hard and Soft IP Cores

Edinburgh, Scotland - November 1, 1999 - Mentor Graphics® Corporation (NASDAQ:MENT) and Synopsys Inc. (NASDAQ:SNPS) today released the jointly developed OpenMORE (Open Measure of Reuse Excellence) reference assessment program for evaluating the reusability of hard and soft intellectual property (IP) cores for system-on-chip (SoC) designs. The assessment program addresses the need for a common reference measurement guide for reusability. Delivering on the commitment made by Synopsys' Chairman and CEO Aart de Geus and Mentor's President and CEO Walden "Wally" Rhines at the Design Automation Conference in June, the two companies have made the OpenMORE assessment program available to the industry at no charge from the Web site: http://www.openmore.com.

OpenMORE is a practical, easy-to-use reference guide and assessment tool supporting the industry's need for rapid adoption of the best design reuse practices for both hard and soft IP. OpenMORE is based on the widely used Reuse Methodology Manual (RMM) Second Edition co-authored by Synopsys and Mentor and the original MORE assessment tool introduced last year by Synopsys. It also includes key specifications from the Virtual Socket Interface Alliance (VSIA) deliverables documentation. In developing OpenMORE, Mentor and Synopsys engaged with IP customers, IP developers and key industry groups including; VSIA, Virtual Chip Exchange (VCX), Design and Reuse (D&R) and Reusable Application-Specific Intellectual Property Developers (RAPID), to ensure that OpenMORE will serve the broader industry's need for a common reference score for IP reusability.

OpenMORE Serves IP Users and Providers
"At Infineon, we found that OpenMORE has proven to be a very useful tool for SoC design," said Joel LeLan, IP group manager of Infineon - R&D Center located in San Jose, California. "We plan on continuing to use it to evaluate the quality of IP blocks."

IP vendors working with Synopsys agree. "IP users are faced with a complex set of issues when purchasing cores, including licensing, business models, design methodology, vendor qualification, core quality, reusability and interoperability," said Wayne Cantwell, president, Semiconductor IP Division at Phoenix Technologies located in San Jose, California. "Common references such as OpenMore will help the industry by clarifying the methodology aspects of the IP buying process."

Industry Groups Agree on Need for Quality Standards
Responding to the concerns of their constituents, the major organizations serving the SoC industry -- VCX, VSIA and D&R -- have all independently determined that quality standards for IP need to be established and have active initiatives in this area.

"OpenMORE has been carefully analyzed by Design and Reuse and our partners who often have different IP requirements, and overall we have concluded that this initiative is extremely beneficial," stated Gabriele Saucier, general manager, Design and Reuse. "We especially appreciate that this initiative is open so that everyone has access to it as well as the reference documentation from the RMM and VSIA."

"VCX welcomes OpenMORE. This method allows any IP vendor to establish a measurement of IP reuse capability," said Andy Travers, CEO of VCX. "This will help the IP industry move to a higher quality level and is consistent with VCX objectives in improving the quality and consistency of IP information and enabling the business and legal processes required for IP trade."

"We are pleased that Synopsys and Mentor Graphics are adopting the VSIA deliverables specifications into OpenMORE, beginning with hard IP. This encourages best practices for virtual component (VC) development and delivery," said Mark Birnbaum, member of the VSIA Executive Staff and director, Strategic Technology, Fujitsu Microelectronics, Inc. of San Jose, California. "Our members have indicated that VC quality is a key area of interest and VSIA has launched a study group to address it. We support best practices which improve VC quality."

Availability and Use of OpenMORE
OpenMORE is available to everyone free of charge by downloading the program from a jointly sponsored Web site: http://www.openmore.com.

After downloading the spreadsheet, assessment data can be added by the user, usually an IP design engineer or engineering team. OpenMORE prompts the user to determine how closely the approximately 180 rules and guidelines for soft IP, or 90 rules and guidelines for hard IP described in the RMM and VSIA deliverables specifications were followed. OpenMORE then uses assigned weightings and percentages to calculate an OpenMORE score. The higher the percentage score, the greater the confidence IP customers will have that the IP core will readily integrate into a SoC design.

About the Reuse Methodology Manual Second Edition
The first edition of the RMM, co-authored by Michael Keating of Synopsys' Design Reuse Group and Pierre Bricaud of the Mentor Inventra IP Division, was the catalyst for the concept of MORE. This book also highlights the physical design flow and its significance in reuse methodologies. Their latest collaboration, RMM Second Edition, is an expanded 300-page manual, available from Kluwer Academic Publishers (http://www.wkap.nl/). It incorporates additional design guidelines that cover low-power design, design reuse, guidelines for verification and soft, firm and hard IP reuse. These guidelines and design examples provide the underlying methodology to establish a best-practice IP reuse process for SoC designs.

About the VSIA Deliverables Documentation
VSIA has recently published the deliverables documents summarizing the results of a number of its working groups. OpenMORE adopts an initial subset of these "mandatory" and "recommended" deliverables and OpenMORE "rules" and "guidelines" respectively. OpenMORE incorporates the hard deliverable specifications of the Virtual Component Transfer (VCT), Implementation/Verification (I/V) and Test (TST) working groups. The complete Deliverables Documentation Version 2.0 rev 08/02/99 is available from the VSIA Web site: http://www.vsi.org.

About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $500 million and employs approximately 2,600 people worldwide. Company headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.

About Synopsys, Inc.
Synopsys Inc. (Nasdaq: SNPS), is the world's leading supplier of electronic design automation (EDA) solutions to the global electronics market. The company provides comprehensive design technologies to creators of advanced integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting services and support to its customers to streamline the overall design process and accelerate time-to-market. Additional information about Synopsys is available at http://www.synopsys.com.

### 

Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Synopsys is a registered trademark of Synopsys Inc. All other company or product names are the registered trademarks or trademarks of their respective owners.
 

For more information, please contact:
Mentor Graphics Contact Lorie Bowlby Public Relations 408.487.7263 lorie_bowlby@mentor.com Synopsys Contact Troy Wood Public Relations 650.584.5717 twood@synopsys.com	Public Relations Contact Janet Martin The Benjamin Group 408.559.6090 janet_martin@benjamingroup.com Public Relations Contact Judy Erkanat The Hoffman Agency 408.975.3072 jerkanat@hoffman.com

 

Previous Page