Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2
eSilicon CEO sees new ASIC landscape
(02/08/2009 6:55 PM EST)
SUNNYVALE, Calif. -- The current IC downturn has already taken its toll on the semiconductor industry in 2009.
And it's only February. Most--if not all--chip makers are bracing for tough economic conditions for the remainder of this year and perhaps beyond.
One semiconductor and EDA veteran sees a ray of hope. Just think positive, said Jack Harding, president, chief executive and chairman of eSilicon Corp. (Sunnyvale, Calif.), a fabless ASIC vendor.
''I've never been a doomsdayer,'' Harding said at the company's headquarters here. ''We'll get through it.''
There is still plenty of IC design activity going on despite market conditions. And surprisingly, there is even movement at the bleeding-edge of design. ''Right now, we're shipping 65-nm,'' he said. ''We're designing 40-nm. We're even getting quotes for 28-nm.''
Despite his upbeat sentiments, Harding also disclosed some sobering news about ASICs and the IC market as a whole. "The ASIC business will become fabless one day, with one or two exceptions,'' he said.
The ''two exceptions'' to the rule could end up being Korea's Samsung Electronics Co. Ltd. and Japan's Toshiba Corp., he said. Both vendors will continue to own fabs.
E-mail This Article | Printer-Friendly Page |
|
Related News
- Fabless ASIC startup eSilicon raises $6 million in funding
- Intel signs 7 out of top 10 fabless companies, sees 18A test chip
- eSilicon Announces Production Qualification of 5G Infrastructure ASIC
- eSilicon Tapes Out 7nm 400G Gearbox/Retimer Test ASIC
- eSilicon builds momentum as a strong tier one FinFET ASIC supplier
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X