HMAC-SHA-2 (224/256/384/512) 100 Million Trace DPA Resistant Crypto Accelerato
Cadence Incisive Verification IP Portfolio Delivers 'All-in-One' Flexibility and Higher Value for SoC Developers
SAN JOSE, Calif. -- Feb 23, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced availability of a new single-license model that grants verification teams access to the extensive Cadence® Incisive® Verification IP (VIP) Portfolio.
The single-license model provides verification teams flexible, cost-effective access to Open Verification Methodology (OVM)-compliant, multi-language VIP for dozens of commonly used protocols.
Under the new model, users purchase a single license to get access to the growing library of metric-driven and assertion-based verification IP from Cadence. This single license can be used to check-out any of the Cadence VIP resources into a user's verification environment and can be reconfigured on a moment-to-moment basis, providing access to new technologies and protocol VIP as they are released. VIP implementation services are available to further speed time to productivity.
"The flexibility of a single multi-language VIP Portfolio that can be used for a variety of protocols and technologies as needed on a daily basis allows SiRF to optimize our verification IP investment," said Mohammed E. Haque, ASIC DV lead at SiRF Technology. "The ability to draw on one license for new protocols and features as needed speeds productivity and allows earlier verification of new IPs."
Cadence VIP supports protocols used widely in wireless, networking, storage, multimedia, and automotive technologies. Having the full force of the broad Cadence portfolio of VIP at their fingertips will help system-on-chip (SoC) integrators quickly build and regress verification environments and take advantage of the deep specification expertise built into each Cadence VIP component. When deployed with Incisive Enterprise Simulator or Incisive Enterprise Specman Elite® Testbench, Incisive Formal Verifier, and Incisive Enterprise Manager in concert with the unique metric-driven Compliance Management System, VIP Portfolio users can increase their confidence that their SoC will meet protocol standards.
"The introduction of portfolio licensing for Incisive VIP is a significant step forward in providing easier-to-implement, OVM-enabled, metric-driven verification methodology," said Michal Siwinski, marketing group director of Enterprise Verification at Cadence. "We believe that out-of-the-box solutions such as Incisive verification IP will help our customers meet their end-users' growing demands for predictable time to market and quality, while improving engineering team productivity."
Also today, Cadence announced the release of open source libraries for e and SystemC languages to support the Open Verification Methodology (OVM), extending the OVM beyond SystemVerilog support.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Design Systems, Inc. Hot IP
Cadence Design Systems, Inc. Hot Verification IP
Related News
- Cadence Delivers 13 New VIP and Expands System VIP Portfolio to Accelerate Automotive, Hyperscale Data Center and Mobile SoC Verification
- Cadence Unveils New Palladium Z2 Apps with Industry's First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification
- Cadence Accelerates Industrial, Automotive, Hyperscale Data Center, and Mobile SoC Verification with Expanded VIP and System VIP Portfolio
- Synopsys Delivers Industry's First USB 3.2 Verification IP and Test Suite for Higher Performance USB Designs
- Cadence Delivers Industry's First Design and Verification IP for MIPI SoundWire v1.1 High Quality Audio Solutions
Breaking News
- Europe Leaps Ahead in Global AI Arms Race, Joining $20 Million Investment in NeuReality to Advance Affordable, Carbon-Neutral AI Data Centers
- Synopsys Showcases EDA Performance and Next-Gen Capabilities with NVIDIA Accelerated Computing, Generative AI and Omniverse
- Spectral Releases Advanced Quality Assurance & Data Analytics tool to validate advanced node Memory Compilers
- TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
- After TSMC fab in Japan, advanced packaging facility is next
Most Popular
- After TSMC fab in Japan, advanced packaging facility is next
- HBM3 Initially Exclusively Supplied by SK Hynix, Samsung Rallies Fast After AMD Validation, Says TrendForce
- Alphawave Semi Demonstrates 3nm Silicon-Proven 24Gbps Universal Chiplet Express (UCIe) Subsystem for High-Performance AI Infrastructure
- Weebit Nano to demo its ReRAM technology on GlobalFoundries' 22FDX® platform
- We'll Need Many More Fabs to Meet $1 Trillion by 2030 Goal
E-mail This Article | Printer-Friendly Page |