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SynTest rolls out design-for-test software to reduce chip-testing costs
By Semiconductor Business News
October 30, 2001 (3:08 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011030S0043
BALTIMORE -- During the International Test Conference (ITC) here today, SynTest Technologies Inc. rolled out a new design-for-test (DFT) software line that promises to reduce chip-testing costs. The Sunnyvale, Calif.-based company announced TurboDFT, a software product that integrates test-ready blocks and intellectual property (IP) cores for use in testing system-on-a-chip and other complex ICs. TurboDFT works with any test-ready blocks or cores, such as scan cores, logic, memory or analog BIST cores, or boundary scan (JTAG) cores. The software accepts RTL, gate-level, and mixed-level design descriptions. "Our customers are increasingly doing more designs with test-ready blocks and cores," said Ravi Apte, vice president of marketing and business development at SynTest. "One of the most time-consuming processes is manually stitching together the intellectual property cores from different sources and in different forms, while maintaining the design's testability," he said. "TurboDFT makes this process easier by automatically integrating the cores and generating top-level test benches," he said. "We believe TurboDFT can shave weeks from this otherwise tedious manual process, and this could be a 10% or 20% saving in time over the manual process for complex designs." TurboDFT runs on Sun Solaris, HP-UX and Linux platforms. It supports Verilog and VHDL designs. It is available now for $50,000. Separately, the company also rolled out TurboDebug-PCB. The software detects, locates and diagnoses interconnect faultson printed circuit boards.